Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
Table 6-11. SYS_NMI_CTLSTAT Register Description (continued)
BIT FIELD TYPE RESET DESCRIPTION
0 CS_SRC RW 1h
0b = Disables CS interrupt as a source of NMI
1b = Enables CS interrupt as a source of NMI
6.6.2 Device-Level User Interrupts
Table 6-12 lists the various interrupt sources and their connection to the NVIC inputs
NOTE
Some sources may have multiple interrupt conditions, in which case the appropriate interrupt
status/flag register of the source must be examined to differentiate between the generating
conditions.
Table 6-12. NVIC Interrupts
NVIC INTERRUPT INPUT SOURCE FLAGS IN SOURCE
INTISR[0] PSS
(1)
INTISR[1] CS
(1)
INTISR[2] PCM
(1)
INTISR[3] WDT_A
INTISR[4] FPU_INT
(2)
Combined interrupt from flags in the FPSCR (part of Cortex-M4 FPU)
INTISR[5] Flash Controller Flash Controller interrupt flags
INTISR[6] COMP_E0 Comparator_E0 interrupt flags
INTISR[7] COMP_E1 Comparator_E1 interrupt flags
INTISR[8] Timer_A0 TA0CCTL0.CCIFG
INTISR[9] Timer_A0 TA0CCTLx.CCIFG (x = 1 through 4), TA0CTL.TAIFG
INTISR[10] Timer_A1 TA1CCTL0.CCIFG
INTISR[11] Timer_A1 TA1CCTLx.CCIFG (x = 1 through 4), TA1CTL.TAIFG
INTISR[12] Timer_A2 TA2CCTL0.CCIFG
INTISR[13] Timer_A2 TA2CCTLx.CCIFG (x = 1 through 4), TA2CTL.TAIFG
INTISR[14] Timer_A3 TA3CCTL0.CCIFG
INTISR[15] Timer_A3 TA3CCTLx.CCIFG (x = 1 through 4), TA3CTL.TAIFG
INTISR[16] eUSCI_A0 UART/SPI mode Tx/Rx/Status Flags
INTISR[17] eUSCI_A1 UART/SPI mode Tx/Rx/Status Flags
INTISR[18] eUSCI_A2 UART/SPI mode Tx/Rx/Status Flags
INTISR[19] eUSCI_A3 UART/SPI mode Tx/Rx/Status Flags
INTISR[20] eUSCI_B0 SPI/I
2
C mode Tx/Rx/Status Flags (I
2
C in multi-slave mode)
INTISR[21] eUSCI_B1 SPI/I
2
C mode Tx/Rx/Status Flags (I
2
C in multi-slave mode)
INTISR[22] eUSCI_B2 SPI/I
2
C mode Tx/Rx/Status Flags (I
2
C in multi-slave mode)
INTISR[23] eUSCI_B3 SPI/I
2
C mode Tx/Rx/Status Flags (I
2
C in multi-slave mode)
INTISR[24] ADC14 IFG[0-31], LO/IN/HI-IFG, RDYIFG, OVIFG, TOVIFG
INTISR[25] Timer32_INT1 Timer32 Interrupt for Timer1
INTISR[26] Timer32_INT2 Timer32 Interrupt for Timer2
INTISR[27] Timer32_INTC Timer32 Combined Interrupt
INTISR[28] AES256 AESRDYIFG
INTISR[29] RTC_C OFIFG, RDYIFG, TEVIFG, AIFG, RT0PSIFG, RT1PSIFG
INTISR[30] DMA_ERR DMA error interrupt
(1) This source can also be mapped to the system NMI. Refer to the MSP432P4xx Family Technical Reference Manual for more details.
(2) The FPU of the Cortex-M4 can generate interrupts due to multiple floating point exceptions. It is the responsibility of software to process
and clear the interrupt flags in the FPSCR.
80 Detailed Description Copyright © 2015, Texas Instruments Incorporated
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