Datasheet

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A1 A2
A3
A4
A5 A6
A7
A8 A9
B1 B2
B3
B4
B5 B6
B7
B8 B9
C1 C2
D1 D2 D4
D5 D6
D7
D8 D9
E1 E2 E4
E5 E6
E7
E8 E9
F1 F2 F4
F5 F8 F9
G1 G2 G4
G5 G8 G9
J1 J2 J4
J5 J6
J7
J8 J9
H1 H2 H4
H5 H6
H7
H8 H9
C4
C5 C6
C7
C8 C9
D3
E3
F3
G3
J3
H3
F6
G6
F7
G7
P1.0
SWCLKTCK
PJ.5
P7.3
PJ.3
RSTn/NMI
P6.5 P6.4 P6.2
P1.1
SWDIOTMS
PJ.4
P7.2
P7.0
P6.7
P6.6
P1.5
VCORE
P1.2 P7.1
DVSS3
P5.5 P5.7
P1.6
DVCC1
P1.4
P5.3 P5.4 P5.6
P1.7
VSW
P5.0
P5.1 P5.2
P2.1 DVSS1
P4.7
P2.5 P2.6
P8.1
P3.2 P3.5 P4.2 P4.3 P4.4
P2.7
P7.5 P8.0 P3.1 P3.4 P3.7 P6.1 P4.1 P4.0
P7.4
P7.6
P3.0 P3.3 P3.6 PJ.0 PJ.1
DCOR
P6.0
PJ.2
P6.3
DVCC2
AVCC2
P1.3
AVSS2
P2.2
P2.0
AVSS3
DVSS2
P2.4
P2.3
AVSS1
AVCC1
P4.5
P7.7
P4.6
MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
Figure 4-2 shows the pinout of the 80-pin ZXH package.
Notes:
1. Glitch filter is implemented on the following 8 digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
2. UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD
3. SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI
4. I
2
C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL
Figure 4-2. 80-Pin ZXH Package (Top View)
8 Terminal Configuration and Functions Copyright © 2015, Texas Instruments Incorporated
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