Datasheet

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MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
6.6.1.1 NMI Control and Status Register [Address = E004_3004h]
Figure 6-12. SYS_NMI_CTLSTAT Register
31 30 29 28 27 26 25 24
Reserved
r r r r r r r r
23 22 21 20 19 18 17 16
Reserved PIN_FLG PCM_FLG PSS_FLG CS_FLG
r r r r rw-0 r-0 r-0 r-0
15 14 13 12 11 10 9 8
Reserved
r r r r r r r r
7 6 5 4 3 2 1 0
Reserved PIN_SRC PCM_SRC PSS_SRC CS_SRC
r r r r rw-0 rw-1 rw-1 rw-1
Table 6-11. SYS_NMI_CTLSTAT Register Description
BIT FIELD TYPE RESET DESCRIPTION
31-20 Reserved R 0h
Reserved. Reads return 0h
19 PIN_FLG RW 0h
0b = Indicates the RSTn/NMI pin was not the source of NMI
1b = Indicates the RSTn/NMI pin was the source of NMI
18 PCM_FLG R 0h
0b = Indicates the PCM interrupt was not the source of NMI
1b = Indicates the PCM interrupt was the source of NMI
This flag gets auto-cleared when the corresponding source flag in the PCM is
cleared
17 PSS_FLG R 0h
0b = Indicates the PSS interrupt was not the source of NMI
1b = Indicates the PSS interrupt was the source of NMI
This flag gets auto-cleared when the corresponding source flag in the PSS is
cleared
16 CS_FLG R 0h
0b = Indicates CS interrupt was not the source of NMI
1b = Indicates CS interrupt was the source of NMI
This flag gets auto-cleared when the corresponding source flag in the CS is
cleared
15-4 Reserved R 0h Reserved. Reads return 0h
3 PIN_SRC
(1)(2)
RW 0h
0b = Configures the RSTn/NMI pin as a source of POR Class Reset
1b = Configures the RSTn/NMI pin as a source of NMI
Note: Setting this bit to 1 prevents the RSTn pin from being used as a reset.
An NMI is triggered by the pin only if a negative edge is detected.
2 PCM_SRC RW 1h
0b = Disbles the PCM interrupt as a source of NMI
1b = Enables the PCM interrupt as a source of NMI
1 PSS_SRC RW 1h
0b = Disables the PSS interrupt as a source of NMI
1b = Enables the PSS interrupt as a source of NMI
(1) When the device enters LPM3/LPM4 modes of operation, the functionality selected by this bit will be retained. If selected as an NMI,
activity on this pin in LPM3/LPM4 will wake the device and process the interrupt, without causing a POR. If selected as a Reset, activity
on this pin in LPM3/LPM4 will cause a device level POR
(2) When the device enters LPM3.5/LPM4.5 modes of operation, this bit will always be cleared to 0. In other words, the RSTn/NMI pin will
always assume a reset functionality in LPM3.5/LPM4.5 modes.
Copyright © 2015, Texas Instruments Incorporated Detailed Description 79
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