Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
Table 6-10. Memory Map Access Response (continued)
INSTRUCTION
ADDRESS RANGE DESCRIPTION READ
(1)
WRITE
(1)
FETCH
(1)
0xE000_0000–0xE003_FFFF Internal PPB
(5)
OK OK Error
0xE004_0000–0xE004_0FFF TPIU (External PPB) OK OK Error
0xE004_1000–0xE004_1FFF Reserved Reserved Reserved Error
Reset Controller (External
0xE004_2000–0xE004_23FF OK OK Error
PPB)
0xE004_2400–0xE004_2FFF Reserved Reserved Reserved Error
0xE004_3000–0xE004_33FF SYSCTL (External PPB) OK OK Error
0xE004_3400–0xE004_3FFF Reserved Reserved Reserved Error
0xE004_4000–0xE004_43FF SYSCTL (External PPB) OK OK Error
0xE004_4400–0xE00F_EFFF Reserved Reserved Reserved Error
0xE00F_F000–0xE00F_FFFF ROM Table (External PPB) OK OK Error
0xE010_0000–0xFFFF_FFFF Reserved Error Error Error
(5) Refer to the Cortex®-M4 TRM for details of the memory map of the internal PPB.
6.6 Interrupts
The Cortex-M4 processor on MSP432P401x devices implements an NVIC with 64 external interrupt lines
and 8 levels of priority. From an application perspective, the interrupt sources at the device level are
divided into two classes, the NMI and the User Interrupts. Internally, the CPU exception model handles the
various exceptions (internal and external events including CPU instruction, memory, and bus fault
conditions) in a fixed and configurable order of priority. For details on the handling of various exception
priorities (including CPU reset and fault models), see the ARM-V7M architecture reference manual at
www.arm.com.
6.6.1 NMI
The NMI input of the NVIC has the following possible sources
• External NMI pin (if configured in NMI mode)
• Oscillator fault condition
• Power Supply System (PSS) generated interrupts
• Power Control Manager (PCM) generated interrupts
The source that finally feeds the NMI of the NVIC is configured through the NMI Control register,
explained in Section 6.6.1.1.
78 Detailed Description Copyright © 2015, Texas Instruments Incorporated
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