Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
6.3.2.3.3 SRAM Bank Retention Control Register (Address = E004_3018h)
This register controls which bank of the SRAM is retained when the device enters LPM3 or LPM4 modes.
Any bank that is not enabled for retention will be completely powered down in these modes and will lose
its data
Figure 6-10. SYS_SRAM_BANKRET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved SRAM
_RDY
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved BNK7_ BNK6_ BNK5_ BNK4_ BNK3_ BNK2_ BNK1_ BNK0_
RET RET RET RET RET RET RET RET
r r r r r r r r rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r-1
Table 6-7. SYS_SRAM_BANKRET Register Description
BIT FIELD TYPE RESET DESCRIPTION
31-17 Reserved R 0h Reserved. Reads return 0h
16 SRAM_RDY
(1)
R 0h
1b = SRAM is ready for accesses. All SRAM banks are enabled or disabled for
retention according to values of bits 7:0 of this register
0b = SRAM banks are being set up for retention. Entry into LPM3, LPM4 should
not be attempted until this bit is set to 1.
15-8 Reserved R 0h Reserved. Reads return 0h
7 BNK7_RET
(2)(3)
RW 0h
0b = Bank7 of the SRAM is not retained in LPM3 or LPM4
1b = Bank7 of the SRAM is retained in LPM3 or LPM4
6 BNK6_RET
(2)
,
(3)
RW 0h
0b = Bank6 of the SRAM is not retained in LPM3 or LPM4
1b = Bank6 of the SRAM is retained in LPM3 or LPM4
5 BNK5_RET
(2)(3)
RW 0h
0b = Bank5 of the SRAM is not retained in LPM3 or LPM4
1b = Bank5 of the SRAM is retained in LPM3 or LPM4
4 BNK4_RET
(2)(3)
RW 0h
0b = Bank4 of the SRAM is not retained in LPM3 or LPM4
1b = Bank4 of the SRAM is retained in LPM3 or LPM4
3 BNK3_RET
(2)
,
(3)
RW 0h
0b = Bank3 of the SRAM is not retained in LPM3 or LPM4
1b = Bank3 of the SRAM is retained in LPM3 or LPM4
2 BNK2_RET
(2)(3)
RW 0h
0b = Bank2 of the SRAM is not retained in LPM3 or LPM4
1b = Bank2 of the SRAM is retained in LPM3 or LPM4
1 BNK1_RET
(2)(3)
RW 0h
0b = Bank1 of the SRAM is not retained in LPM3 or LPM4
1b = Bank1 of the SRAM is retained in LPM3 or LPM4
0 BNK0_RET R 1h Bank0 is always retained in LPM3, LPM4 and LPM3.5 modes of operation
(1) This bit will automatically be set to 0 whenever any of the BNKx_RET bits in this register are changed. It will set back to 1 after the
SRAM controller has recognized the new BNKx_RET values.
(2) Value of this bit is a don't care when the device enters LPM3.5 or LPM4.5 modes of operation. It will always get reset and the SRAM
block associated with this bit will not retain its contents.
(3) Writes to this bit are allowed ONLY when the SRAM_RDY bit of this register is set to 1. If the SRAM_RDY bit is 0, writes to this bit will
be ignored.
74 Detailed Description Copyright © 2015, Texas Instruments Incorporated
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