Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
6.3.1.1.1 Flash Size Register (Address = 0xE004_3020h)
This register reflects the size of flash main memory available on the device.
Figure 6-6. SYS_FLASH_SIZE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIZE
r r r r r r r r r r r r r r-1 r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIZE
r r r r r r r r r r r r r r r r
Table 6-3. SYS_FLASH_SIZE Register Description
BIT FIELD TYPE RESET DESCRIPTION
31-0 SIZE R Variable Indicates the size (in bytes) of the flash main memory on the device. This is
divided equally between the two banks.
6.3.1.2 Flash Information Memory (0x0020_0000 to 0x0020_3FFF)
The flash information memory region is 16KB. Flash information memory consists of four sectors of 4KB
each, with a minimum erase granularity of 4KB (1 sector). The information memory can be viewed as two
independent blocks of 8KB each, which allows read or execute from one block while the other block is
undergoing a program or erase operation. Table 6-4 describes different regions of flash information
memory and the contents of each of the regions. The flash information memory region that contains the
device descriptor (TLV) is factory configured for protection again write or erase operations.
Table 6-4. Flash Information Memory Regions
WRITE AND ERASE
REGION ADDRESS RANGE CONTENTS
PROTECTED?
Bank 0, Sector 0 0x0020_0000–0x0020_0FFF Flash Boot-override Mailbox No
Bank 0, Sector 1 0x0020_1000–0x0020_1FFF Device Descriptor (TLV) Yes
Bank 1, Sector 0 0x0020_2000–0x0020_2FFF TI BSL No
Bank 1, Sector 1 0x0020_3000–0x0020_3FFF TI BSL No
6.3.1.3 Flash Operation
The flash memory provides multiple read and program modes of operation that the application can deploy.
Up to 128 bits (memory word width) can be programmed (set from 1 to 0) in a single program operation.
Although the CPU data buses are 32 bits wide, the flash can buffer 128-bit write data before initiating flash
programming, thereby making it more seamless and power efficient for software to program large blocks
of data at a time. In addition, the flash memory also supports a burst write mode that takes less time when
compared to programming words individually. Refer to Flash Memory for information on timing
parameters.
The flash main and information memory regions offer write/erase protection control at a sector granularity
to enable software to optimize operations like mass erase while protecting certain regions of the flash. In
low-power modes of operation, the flash memory is disabled and put in a power-down state to minimize
leakage.
For details on the flash memory and its various modes of operation and configuration, refer to the Flash
Controller chapter in the MSP432P4xx Family Technical Reference Manual (SLAU356).
68 Detailed Description Copyright © 2015, Texas Instruments Incorporated
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