Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
6.2.4 Debug and Trace Peripheral Zone
This zone maps the internal as well as external PPB regions of the Cortex-M4. The following peripherals
are mapped to this zone
• Core and System debug control registers (internal PPB)
• NVIC and other registers in the System Control space of the Cortex-M4 (internal PPB)
• FPB, DWT, ITM (internal PPB)
• TPIU, Debug ROM table (external PPB)
• Reset Controller (external PPB)
• System Controller (external PPB)
Table 6-2. Debug Zone Memory Map
ADDRESS RANGE MODULE OR PERIPHERAL REMARKS
0xE000_0000–0xE000_0FFF ITM Internal PPB
0xE000_1000–0xE000_1FFF DWT Internal PPB
0xE0000_2000–0xE000_2FFF FPB Internal PPB
0xE000_3000–0xE000_DFFF Reserved Internal PPB
0xE000_E000–0xE000_EFFF Cortex-M4 System Control Space Internal PPB
0xE000_F000–0xE003_FFFF Reserved Internal PPB
0xE004_0000–0xE004_0FFF TPIU External PPB
0xE004_1000–0xE004_1FFF Reserved External PPB
0xE004_2000–0xE004_23FF Reset Controller External PPB
0xE004_2400–0xE004_2FFF Reserved External PPB
0xE004_3000–0xE004_33FF System Controller External PPB
0xE004_3400–0xE004_3FFF Reserved External PPB
0xE004_4000–0xE004_43FF System Controller External PPB
0xE004_4400–0xE00F_EFFF Reserved External PPB
0xE00F_F000–0xE00F_FFFF ROM Table (External PPB) External PPB
0xE010_0000–0xFFFF_FFFF Reserved Vendor Space
NOTE
Refer to the Cortex-M4 TRM for the address maps of the ARM modules listed above
NOTE
The region from 0xE004_4000–0xE004_43FF is reserved for System Controller registers.
These registers are detailed in various sections of this data sheet
6.3 Memories on the MSP432P401x
The MSP432P401x devices include flash and SRAM memories for general application purposes. In
addition, the devices include a backup memory (a portion of total available SRAM) that is retained in low-
power modes.
6.3.1 Flash Memory
The MSP432P401x devices include a high-endurance low-power flash memory that supports up to 20000
write and erase cycles. The flash memory is 128 bits wide thereby enabling high code execution
performance by virtue of each fetch returning up to four 32-bit instructions (or up to eight 16-bit
instructions). The flash is further divided into two types of subregions: Main Memory and Information
Memory.
66 Detailed Description Copyright © 2015, Texas Instruments Incorporated
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