Datasheet

PRODUCTPREVIEW
MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
5.10.12 Emulation and Debug
Table 5-55. JTAG
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
f
TCK
TCK clock frequency 0 10 MHz
t
TCK
TCK clock period 100 ns
t
TCK_LOW
TCK clock low time t
TCK
/2 ns
t
TCK_HIGH
TCK clock high time t
TCK
/2 ns
t
TCK_RISE
TCK rise time 0 10 ns
t
TCK_FALL
TCK fall time 0 10 ns
t
TMS_SU
TMS setup time to TCK rise 28 ns
t
TMS_HLD
TMS hold time from TCK rise 4 ns
t
TDI_SU
TDI setup time to TCK rise 18 ns
t
TDI_HLD
TDI hold time from TCK rise 4 ns
t
TDO_ZDV
TCK fall to data valid from high impedance TBD 42 ns
t
TDO_DV
TCK fall to data valid from data valid TBD 40 ns
t
TDO_DVZ
TCK fall to high impedance from data valid TBD 33 ns
Copyright © 2015, Texas Instruments Incorporated Specifications 59
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