Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
5.10.11 Memories
Table 5-53. Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
DVCC
PGM/ERS
Supply voltage for program or erase 1.62 3.7 V
I
PGM/ERS, AVG
Average supply current from DVCC during program or erase TBD 35 mA
I
PGM/ERS, PEAK
Peak supply current from DVCC during program or erase 50 mA
N
Endurance
Program or erase endurance 10
5
cycles
t
Retention
Data retention duration T
J
= TBD 20 years
t
word
Word program time without preverify (VER_PRE = 0)
(1)
37 39 µs
t
word, ver
Word program time with preverify (VER_PRE = 1)
(1)
62 63 µs
t
block, 0
Block program time for the first data 11 12 µs
t
block, 1-(N-1)
Block program time for each additional data, except for last data 8 9 µs
t
block, N
Block program time for the last data 13 14 µs
t
ERS
Segment or mass erase time 2.5 3 ms
t
ers2ersver
Erase to erase verify mode transition time 2 3 µs
t
nrd2ersver
Normal read to erase verify mode transition time 11 12 µs
t
pgm2pgmver
Program to program verify mode transition time 13.5 15 µs
t
nrd2pgmver
Normal read to program verify mode transition time 13.5 15 µs
(1) After verify enabled (VER_PST = 1).
Table 5-54. SRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCORE = 1.2 V 80
I
SRAM_EN
Current consumption of one SRAM bank when enabled nA
VCORE = 1.4 V 290
VCORE = 1.2 V 27
I
SRAM_RET
Current consumption of one SRAM bank under retention nA
VCORE = 1.4 V 31
t
SRAM_EN, one
Time taken to enable one SRAM bank 4 5 µs
t
SRAM_DIS, one
Time taken to disable one SRAM bank 4 5 µs
t
SRAM_EN, all
Time taken to enable all SRAM banks except Bank-0 7 8 µs
t
SRAM_DIS, all
Time taken to disable all SRAM banks except Bank-0 4 5 µs
58 Specifications Copyright © 2015, Texas Instruments Incorporated
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