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UCLK
CKPL = 0
CKPL = 1
SOMI
SIMO
t
SU,SI
t
HD,SI
t
VALID,SO
t
HD,SO
t
LOW/HIGH
1/f
UCxCLK
t
LOW/HIGH
t
STE,DIS
t
STE,ACC
STE
t
STE,LEAD
t
STE,LAG
UCMODEx = 01
UCMODEx = 10
MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
Figure 5-6. SPI Slave Mode, CKPH = 1
Table 5-50. eUSCI (I
2
C Mode), Recommended Operating Conditions
PARAMETER TEST CONDITIONS V
CORE
V
CC
MIN TYP MAX UNIT
Internal: SMCLK 1.2 V 12
eUSCI input clock
f
eUSCI
External: UCLK MHz
frequency
1.4 V 24
Duty cycle = 50% ± 10%
f
SCL
SCL clock frequency 1 MHz
Copyright © 2015, Texas Instruments Incorporated Specifications 55
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