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UCLK
CKPL = 0
CKPL = 1
SOMI
SIMO
t
SU,SI
t
HD,SI
t
VALID,SO
t
LOW/HIGH
1/f
UCxCLK
t
LOW/HIGH
t
STE,DIS
t
STE,ACC
STE
t
STE,LEAD
t
STE,LAG
UCMODEx = 01
UCMODEx = 10
t
HD,SO
MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
Table 5-49. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
(1)
)
PARAMETER TEST CONDITIONS V
CORE
V
CC
MIN TYP MAX UNIT
1.2 V 1.62 V 65
t
STE,LEAD
STE lead time, STE active to clock ns
1.4 V 3.7 V 45
1.2 V 1.62 V 5
t
STE,LAG
STE lag time, Last clock to STE inactive ns
1.4 V 3.7 V 5
1.2 V 1.62 V 90
STE access time, STE active to SOMI data
t
STE,ACC
ns
out
1.4 V 3.7 V 50
1.2 V 1.62 V 30
STE disable time, STE inactive to SOMI
t
STE,DIS
ns
high impedance
1.4 V 3.7 V 10
1.2 V 1.62 V 8
t
SU,SI
SIMO input data setup time ns
1.4 V 3.7 V 4
1.2 V 1.62 V 7
t
HD,SI
SIMO input data hold time ns
1.4 V 3.7 V 6
1.2 V 1.62 V 50
UCLK edge to SOMI valid,
t
VALID,SO
SOMI output data valid time
(2)
ns
C
L
= 20 pF
1.4 V 3.7 V 10
1.2 V 1.62 V 0
t
HD,SO
SOMI output data hold time
(3)
C
L
= 20 pF ns
1.4 V 3.7 V 0
(1) f
UCxCLK
= 1/2t
LO/HI
with tL
O/HI
≥ max(t
VALID,MO(Master)
+ t
SU,SI(eUSCI)
, t
SU,MI(Master)
+ t
VALID,SO(eUSCI)
).
For the master parameters t
SU,MI(Master)
and t
VALID,MO(Master)
refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-5 and Figure 5-6.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 5-5 and Figure 5-6.
Figure 5-5. SPI Slave Mode, CKPH = 0
54 Specifications Copyright © 2015, Texas Instruments Incorporated
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