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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
5.10.9 eUSCI
Table 5-45. eUSCI (UART Mode), Recommended Operating Conditions
PARAMETER TEST CONDITIONS VCORE VCC MIN TYP MAX UNIT
Internal: SMCLK 1.2 V 12
f
eUSCI
eUSCI input clock frequency External: UCLK MHz
1.4 V 24
Duty cycle = 50% ± 10%
1.2 V 1
BITCLK clock frequency
f
BITCLK
MHz
(equals baud rate in MBaud)
1.4 V 3
Table 5-46. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
UCGLITx = 0 10 40
UCGLITx = 1 25 90
t
t
UART receive deglitch time
(1)
ns
UCGLITx = 2 45 140
UCGLITx = 3 60 190
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch
time can limit the max. useable baud rate. To ensure that pulses are correctly recognized, their duration should exceed the maximum
specification of the deglitch time.
Table 5-47. eUSCI (SPI Master Mode), Recommended Operating Conditions
PARAMETER CONDITIONS V
CC
MIN TYP MAX UNIT
VCORE = 1.2 V 12
SMCLK
f
eUSCI
eUSCI input clock frequency MHz
Duty cycle = 50% ± 10%
VCORE = 1.4 V 24
Table 5-48. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CORE
V
CC
MIN TYP MAX UNIT
UCSTEM = 1,
t
STE,LEAD
STE lead time, STE active to clock 1
UCMODEx = 01 or 10
UCxCLK
cycles
STE lag time, Last clock to STE UCSTEM = 1,
t
STE,LAG
1
inactive UCMODEx = 01 or 10
1.2 V 1.62 V 90
STE access time, STE active to UCSTEM = 0,
t
STE,ACC
ns
SIMO data out UCMODEx = 01 or 10
1.4 V 3.7 V 50
1.2 V 1.62 V 35
STE disable time, STE inactive to UCSTEM = 0,
t
STE,DIS
ns
SIMO high impedance UCMODEx = 01 or 10
1.4 V 3.7 V 10
1.2 V 1.62 V 50
t
SU,MI
SOMI input data setup time ns
1.4 V 3.7 V 25
1.2 V 1.62 V 0
t
HD,MI
SOMI input data hold time ns
1.4 V 3.7 V 0
1.2 V 1.62 V 5
UCLK edge to SIMO valid,
t
VALID,MO
SIMO output data valid time
(2)
ns
C
L
= 20 pF
1.4 V 3.7 V 1
1.2 V 1.62 V 0
t
HD,MO
SIMO output data hold time
(3)
C
L
= 20 pF ns
1.4 V 3.7 V 0
(1) f
UCxCLK
= 1/2t
LO/HI
with tL
O/HI
= max(t
VALID,MO(eUSCI)
+ t
SU,SI(Slave)
, t
SU,MI(eUSCI)
+ t
VALID,SO(Slave)
).
For the slave parameters t
SU,SI(Slave)
and t
VALID,SO(Slave)
refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-3 and Figure 5-4.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 5-3 and Figure 5-4.
52 Specifications Copyright © 2015, Texas Instruments Incorporated
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