Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
Table 5-38. 14-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
1 Msps, ADC14PWRMD = 0 1.8 V to 3.7 V 25
For specified performance of
f
ADC14CLK
MHz
ADC14 linearity parameters
200 ksps, ADC14PWRMD = 2 1.62 V to 3.7 V 5
ADC14RES = 11 16
ADC14RES = 10 14
N
CONVERT
Clock cycles for conversion cycles
ADC14RES = 01 11
ADC14RES = 00 9
t
ADC14ON
Turnon settling time of the ADC See
(1)
100 ns
t
Sample
Sampling time
(2)
R
S
= 200 Ω, C
S
= 10pF 0.215 µs
(1) The condition is that the error in a conversion started after t
ADC14ON
is less than ±0.5 LSB. The reference and input signal are already
settled.
(2) Sampling time should be at-least 4x 1/f
ADC14CLK
.
Table 5-39. 14-Bit ADC, Linearity Parameters, LDO Operation
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
1Msps, ADC14DIF = 0, ADC14VRSEL = 1110
(1)
,
With single-ended input 1.8 V to 3.7 V TBD 75
2.5-V reference, 20-kHz input sine
SINAD dB
1Msps, ADC14DIF = 1, ADC14VRSEL = 1110
(1)
,
With differential input 1.8 V to 3.7 V TBD 80
2.5-V reference, 20-kHz input sine
1Msps, ADC14DIF = 0, ADC14VRSEL = 1110
(1)
,
With single-ended input 1.8 V to 3.7 V TBD 12.1
2.5-V reference, 20-kHz input sine
ENOB bit
1Msps, ADC14DIF = 1, ADC14VRSEL = 1110
(1)
,
With differential input 1.8 V to 3.7 V TBD 13
2.5-V reference, 20-kHz input sine
1.45 V≤ V
R+
- V
R-
≤ AVCC –2.0 2.0
Integral linearity error
E
I
LSB
(INL)
1.2 V < V
R+
- V
R-
< 1.45 TBD TBD
Differential linearity
E
D
–0.99 1.0 LSB
error (DNL)
E
O
Offset error –0.7 ±0.35 0.7 mV
E
G
Gain error –2.0 ±1 2.0 LSB
E
T
Total unadjusted error –10 ±TBD 10 LSB
(1) VeREF- pin should be connected to onboard ground for ADC14VRSEL = 1110.
46 Specifications Copyright © 2015, Texas Instruments Incorporated
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