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MSP432P401R, MSP432P401M
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SLAS826 –MARCH 2015
Table 5-34. Digital Outputs, Normal I/Os
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
I
(OHmax)
= –1 mA
(1)
V
CC
– 0.25 V
CC
2.2 V
I
(OHmax)
= –3 mA
(2)
V
CC
– 0.60 V
CC
V
OH
High-level output voltage V
I
(OHmax)
= –2 mA
(1)
V
CC
– 0.25 V
CC
3.0 V
I
(OHmax)
= –6 mA
(2)
V
CC
– 0.60 V
CC
I
(OLmax)
= 1 mA
(1)
V
SS
V
SS
+ 0.25
2.2 V
I
(OLmax)
= 3 mA
(2)
V
SS
V
SS
+ 0.60
V
OL
Low-level output voltage V
I
(OLmax)
= 2 mA
(1)
V
SS
V
SS
+ 0.25
3.0 V
I
(OLmax)
= 6 mA
(2)
V
SS
V
SS
+ 0.60
1.62 V 20
Port output frequency (with RC
f
Px.y
VCORE = 1.4 V, C
L
= 20 pF, R
L
(4) (5)
2.2 V 24 MHz
load)
(3)
3.0 V 24
1.62 V 40% 60%
Port output duty cycle (with RC
d
Px.y
VCORE = 1.4 V, C
L
= 20 pF, R
L
(4) (5)
2.2 V 40% 60%
Load)
3.0 V 45% 55%
1.62 V 20
f
Port_CLK
Clock output frequency
(3)
VCORE = 1.4 V, C
L
= 20 pF
(5)
2.2 V 24 MHz
3.0 V 24
1.62 V 40% 60%
d
Port_CLK
Clock output duty cycle VCORE = 1.4 V, C
L
= 20 pF
(5)
2.2 V 40% 60%
3.0 V 45% 55%
1.62 V 8
Port output rise time, digital only
t
rise,dig
C
L
= 20 pF
(6)
2.2 V 5 ns
port pins
3.0 V 3
1.62 V 8
Port output fall time, digital only
t
fall,dig
C
L
= 20 pF
(7)
2.2 V 5 ns
port pins
3.0 V 3
1.62 V 8
Port output rise time, port pins
t
rise,ana
C
L
= 20 pF
(6)
2.2 V 5 ns
with shared analog functions
3.0 V 3
1.62 V 8
Port output fall time, port pins
t
fall,ana
C
L
= 20 pF
(7)
2.2 V 5 ns
with shared analog functions
3.0 V 3
(1) The maximum total current, I
(OHmax)
and I
(OLmax)
, for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I
(OHmax)
and I
(OLmax)
, for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
(3) The port can output frequencies at least up to the specified limit - it might support higher frequencies.
(4) A resistive divider with 2 × R1 and R1 = 3.2kΩ between V
CC
and V
SS
is used as load. The output is connected to the center tap of the
divider. C
L
= 20pF is connected to the output to V
SS
.
(5) The output voltage reaches at least 20% and 80% V
CC
at the specified toggle frequency.
(6) Measured between 20% of V
CC
to 80% of V
CC
.
(7) Measured between 80% of V
CC
to 20% of V
CC
.
Copyright © 2015, Texas Instruments Incorporated Specifications 43
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