Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
5.10.5 Digital I/Os
Table 5-33. Digital Inputs (Applies to Both Normal and High-Drive I/Os)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
2.2 V 0.99 1.65
V
IT+
Positive-going input threshold voltage V
3 V 1.35 2.25
2.2 V 0.55 1.21
V
IT–
Negative-going input threshold voltage V
3 V 0.75 1.65
2.2 V 0.32 0.84
V
hys
Input voltage hysteresis (V
IT+
– V
IT–
) V
3 V 0.4 1.0
For pullup: V
IN
= V
SS
R
Pull
Pullup or pulldown resistor 20 35 50 kΩ
For pulldown: V
IN
= V
CC
C
I,dig
Input capacitance, digital only port pins V
IN
= V
SS
or V
CC
3 pF
Input capacitance, port pins shared with
C
I,ana
V
IN
= V
SS
or V
CC
5 pF
analog functions
Normal I/O high-impedance input leakage
I
lkg,ndio
(1) (2)
2.2 V, 3 V –20 +20 nA
current (refer also to and )
High-drive I/O high-impedance input leakage
I
lkg,hdio
(1) (2)
2.2 V, 3 V –20 +20 nA
current (refer also to and )
Ports with interrupt capability and
2.2 V, 3 V 20 ns
without glitch filter
Ports with interrupt capability and
External interrupt timing (external trigger with glitch filter but glitch filter 2.2 V, 3 V 20 ns
t
int
pulse duration to set interrupt flag)
(3)
disabled (GLTFLT_EN = 0)
Ports with interrupt capability and
with glitch filter, Glitch filter enabled 2.2 V, 3 V 2 µs
(GLTFTL_EN = 1)
t
RST
External reset pulse duration on RSTn pin
(4)
2.2 V, 3 V 2 µs
(1) The input leakage current is measured with V
SS
or V
CC
applied to the corresponding pins, unless otherwise noted.
(2) The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t
int
is met. It may be set by trigger signals
shorter than t
int
.
(4) Not applicable if RSTn/NMI pin configured as NMI.
42 Specifications Copyright © 2015, Texas Instruments Incorporated
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