Datasheet

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MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
5.10.2 Reset Timing
Table 5-15. Reset Recovery Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER MIN TYP MAX UNIT
MCLK
t
SOFT
Latency from release of soft reset to first CPU instruction fetch 5
cycles
MCLK
t
HARD
Latency from release of hard reset to release of soft reset 25
cycles
t
POR
Latency from release of device POR to release of hard reset 15 25 µs
Latency from a cold power-up condition to release of device
t
COLDPWR,100 nF
410 1000 µs
POR, C
VCORE
= 100 nF
Latency from a cold power-up condition to release of device
t
COLDPWR,4.7 µF
530 1600 µs
POR, C
VCORE
= 4.7 µF
(1) Refer to Section 6.7.1 for details on the various classes of resets on the device
Table 5-16. External Reset (RSTn) Recovery Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
External reset applied on RSTn pin while the device is in
t
AMLDO0_RSTn, 16MHz
AM_LDO_VCORE0 mode with MCLK = 16 MHz, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
AMLDO1_RSTn, 32MHz
AM_LDO_VCORE1 mode with MCLK = 32 MHz, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
AMLDO1_RSTn, 48MHz
AAM_LDO_VCORE1 mode with MCLK = 48 MHz, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
AMDCDC0_RSTn, 16MHz
AM_DCDC_VCORE0 mode with MCLK = 16 MHz, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
AMDCDC1_RSTn, 48MHz
AM_DCDC_VCORE1 mode with MCLK = 48 MHz, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
AMLF0_RSTn, 128kHz
AM_LF_VCORE0 mode with MCLK = 128 kHz from REFO, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
AMLF0_RSTn, 32kHz
AM_LF_VCORE0 mode with MCLK = 32 kHz from LFXT, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
AMLF1_RSTn, 128kHz
AM_LF_VCORE1 mode with MCLK = 128 kHz from REFO, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
LPM0LDO0_RSTn, 16MHz
LPM0_LDO_VCORE0 mode with MCLK = 16 MHz, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
LPM0LDO1_RSTn, 48MHz
LPM0_LDO_VCORE1 mode with MCLK = 48 MHz, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
LPM0DCDC0_RSTn, 16MHz
LPM0_DCDC_VCORE0 mode with MCLK = 16 MHz, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
LPM0DCDC1_RSTn, 48MHz
LPM0_DCDC_VCORE1 mode with MCLK = 48 MHz, TBD 4 ms
The latency is from release of external reset to start of application code
External reset applied on RSTn pin while the device is in
t
LPM0LF0_RSTn, 128kHz
LPM0_LF_VCORE0 mode with MCLK = 128 kHz from REFO, TBD 4 ms
The latency is from release of external reset to start of application code
Copyright © 2015, Texas Instruments Incorporated Specifications 27
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