Datasheet

PRODUCTPREVIEW
MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
Table 5-14. LPM3.5, LPM4.5 Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
LATENCY
ORIGINAL OPERATING FINAL OPERATING
PARAMETER TEST CONDITIONS UNIT
MODE MODE
TYP MAX
Transition from AM_LDO_VCORE0 to
t
AMLDO0_LPM3.5
(1)
AM_LDO_VCORE0 LPM3.5 22 25 µs
LPM3.5
Transition from AM_DCDC_VCORE0 to
t
AMDCDC0_LPM3.5
(1)
AM_DCDC_VCORE0 LPM3.5 34 47 µs
LPM3.5
Transition from AM_LF_VCORE0 to
t
AMLF0_LPM3.5
(1)
AM_LF_VCORE0 LPM3.5 225 240 µs
LPM3.5
Transition from AM_LDO_VCORE1 to
t
AMLDO1_LPM3.5
(1)
AM_LDO_VCORE1 LPM3.5 22 25 µs
LPM3.5
Transition from AM_DCDC_VCORE1 to
t
AMDCDC1_LPM3.5
(1)
AM_DCDC_VCORE1 LPM3.5 32 45 µs
LPM3.5
Transition from AM_LF_VCORE1 to
t
AMLF1_LPM3.5
(1)
AM_LF_VCORE1 LPM3.5 225 240 µs
LPM3.5
Transition from AM_LDO_VCORE0 to
t
AMLDO0_LPM4.5
(2)
AM_LDO_VCORE0 LPM4.5 22 25 µs
LPM4.5
Transition from AM_DCDC_VCORE0 to
t
AMDCDC0_LPM4.5
(2)
AM_DCDC_VCORE0 LPM4.5 32 45 µs
LPM4.5
Transition from AM_LF_VCORE0 to
t
AMLF0_LPM4.5
(2)
AM_LF_VCORE0 LPM4.5 180 195 µs
LPM4.5
Transition from AM_LDO_VCORE1 to
t
AMLDO1_LPM4.5
(2)
AM_LDO_VCORE1 LPM4.5 22 25 µs
LPM4.5
Transition from AM_DCDC_VCORE1 to
t
AMDCDC1_LPM4.5
(2)
AM_DCDC_VCORE1 LPM4.5 22 25 µs
LPM4.5
Transition from AM_LF_VCORE1 to
t
AMLF1_LPM4.5
(2)
AM_LF_VCORE1 LPM4.5 180 195 µs
LPM4.5
Transition from LPM3.5 to
t
LPM3.5_AMLDO0
(3)
LPM3.5 AM_LDO_VCORE0 0.9 0.95 ms
AM_LDO_VCORE0
Transition from LPM4.5 to
AM_LDO_VCORE0,
t
LPM4.5_AMLDO0_SVSMON,100 nF
(3)
LPM4.5 AM_LDO_VCORE0 1 TBD ms
SVSMH enabled while in LPM4.5,
C
VCORE
= 100 nF
Transition from LPM4.5 to
AM_LDO_VCORE0,
t
LPM4.5_AMLDO0_SVSMON,4.7 µF
(3)
LPM4.5 AM_LDO_VCORE0 TBD TBD ms
SVSMH enabled while in LPM4.5,
C
VCORE
= 4.7 µF
Transition from LPM4.5 to
t
LPM4.5_AMLDO0_SVSMOFF,100 nF
AM_LDO_VCORE0,
LPM4.5 AM_LDO_VCORE0 1.7 TBD ms
(3)
SVSMH disabled while in LPM4.5,
C
VCORE
= 100 nF
Transition from LPM4.5 to
AM_LDO_VCORE0,
t
LPM4.5_AMLDO0_SVSMOFF,4.7 µF
(3)
LPM4.5 AM_LDO_VCORE0 TBD TBD ms
SVSMH disabled while in LPM4.5,
C
VCORE
= 4.7 µF
(1) This is the latency from WFI instruction execution by CPU to LPM3.5 mode entry.
(2) This is the latency from WFI instruction execution by CPU to LPM4.5 mode entry.
(3) This is the latency from I/O wake-up event to start of application code.
26 Specifications Copyright © 2015, Texas Instruments Incorporated
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