Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
Table 5-12. LPM0 Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
LATENCY
ORIGINAL OPERATING FINAL OPERATING
PARAMETER TEST CONDITIONS UNIT
MODE MODE
TYP MAX
Transition from
MCLK
t
AMLDO0_LPM0LDO0
(1)
AM_LDO_VCORE0 LPM0_LDO_VCORE0 AM_LDO_VCORE0 to 1
cycles
LPM0_LDO_VCORE0
Transition from
LPM0_LDO_VCORE0 to MCLK
t
LPM0LDO0_AMLDO0
(2)
LPM0_LDO_VCORE0 AM_LDO_VCORE0 3 4
AM_LDO_VCORE0 cycles
through I/O interrupt
Transition from
MCLK
t
AMDCDC0_LPM0DCDC0
(1)
AM_DCDC_VCORE0 LPM0_DCDC_VCORE0 AM_DCDC_VCORE0 to 1
cycles
LPM0_DCDC_VCORE0
Transition from
LPM0_DCDC_VCORE0 MCLK
t
LPM0DCDC0_AMDCDC0
(2)
LPM0_DCDC_VCORE0 AM_DCDC_VCORE0 3 4
to AM_DCDC_VCORE0 cycles
through I/O interrupt
Transition from
AM_LF_VCORE0 to
LPM0_LF_VCORE0, All MCLK
t
AMLF0_LPM0LF0
(1)
AM_LF_VCORE0 LPM0_LF_VCORE0 1
high frequency clock cycles
sources (DCO, HFXT,
MODOSC) disabled
Transition from
LPM0_LF_VCORE0 to
AM_LF_VCORE0
MCLK
t
LPM0LF0_AMLF0
(2)
LPM0_LF_VCORE0 AM_LF_VCORE0 through I/O interrupt, All 3 4
cycles
high frequency clock
sources (DCO, HFXT,
MODOSC) disabled
Transition from
MCLK
t
AMLDO1_LPM0LDO1
(1)
AM_LDO_VCORE1 LPM0_LDO_VCORE1 AM_LDO_VCORE1 to 1
cycles
LPM0_LDO_VCORE1
Transition from
LPM0_LDO_VCORE1 to MCLK
t
LPM0LDO1_AMLDO1
(2)
LPM0_LDO_VCORE1 AM_LDO_VCORE1 3 4
AM_LDO_VCORE1 cycles
through I/O interrupt
Transition from
MCLK
t
AMDCDC1_LPM0DCDC1
(1)
AM_DCDC_VCORE1 LPM0_DCDC_VCORE1 AM_DCDC_VCORE1 to 1
cycles
LPM0_DCDC_VCORE1
Transition from
LPM0_DCDC_VCORE1 MCLK
t
LPM0DCDC1_AMDCDC1
(2)
LPM0_DCDC_VCORE1 AM_DCDC_VCORE1 3 4
to AM_DCDC_VCORE1 cycles
through I/O interrupt
Transition from
AM_LF_VCORE1 to
LPM0_LF_VCORE1. All MCLK
t
AMLF1_LPM0LF1
(1)
AM_LF_VCORE1 LPM0_LF_VCORE1 1
high frequency clock cycles
sources (DCO, HFXT,
MODOSC) disabled
Transition from
LPM0_LF_VCORE1 to
AM_LF_VCORE1
MCLK
t
LPM0LF1_AMLF1
(2)
LPM0_LF_VCORE1 AM_LF_VCORE1 through I/O interrupt. All 3 4
cycles
high frequency clock
sources (DCO, HFXT,
MODOSC) disabled
(1) This is the latency between execution of WFI instruction by CPU to assertion of SLEEPING signal at CPU output.
(2) This is the latency between I/O interrupt event to deassertion of SLEEPING signal at CPU output.
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