Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
Table 5-4. Current Consumption in Low-Frequency Active Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)(2)(3)(4)(5)
–40°C 25°C 60°C 85°C
EXECUTION
PARAMETER V
CC
UNIT
MEMORY
TYP MAX TYP MAX TYP MAX TYP MAX
2.2 V
I
AM_LF_VCORE0, Flash
(6) (7)
Flash μA
3.0 V 90 570
2.2 V
I
AM_LF_VCORE1, Flash
(6) (7)
Flash μA
3.0 V 95 680
2.2 V
I
AM_LF_VCORE0, SRAM
(8)
SRAM μA
3.0 V
2.2 V
I
AM_LF_VCORE1, SRAM
(8)
SRAM μA
3.0 V
(1) Current measured into V
CC
.
(2) All other input pins tied to 0 V or V
CC
. Outputs do not source or sync any current.
(3) MCLK sourced by REFO at 128 kHz.
(4) All peripherals are inactive.
(5) SRAM banks 0,1 enabled for execution from flash and SRAM banks 0 to 3 enabled for execution from SRAM.
(6) Flash configured to 0 wait states.
(7) Device executing the Dhrystone 2.1 algorithm. Code execution from Flash, stack and data in SRAM.
(8) Device executing the Dhrystone 2.1 algorithm. Code execution from SRAM, stack and data also in SRAM.
Table 5-5. Current Consumption in LDO-Based LPM0 Modes
over recommended operating free-air temperature (unless otherwise noted)
(1)(2)(3)(4)(5)(6)
MCLK = MCLK = MCLK = MCLK = MCLK = MCLK =
8 MHz 16 MHz 24 MHz 32 MHz 40 MHz 48 MHz
PARAMETER V
CC
UNIT
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
2.2 V
I
LPM0_LDO_VCORE0
µA
3.0 V 700 1350
2.2 V
I
LPM0_LDO_VCORE1
µA
3.0 V 1130 1900
(1) MCLK sourced by DCO.
(2) Current measured into V
CC
.
(3) All other input pins tied to 0 V or V
CC
. Outputs do not source or sync any current.
(4) CPU is OFF, Flash or SRAM not being accessed.
(5) All SRAM banks kept active.
(6) All peripherals are inactive.
Table 5-6. Current Consumption in DC-DC-Based LPM0 Modes
over recommended operating free-air temperature (unless otherwise noted)
(1)(2)(3)(4)(5)(6)
MCLK = MCLK = MCLK = MCLK = MCLK = MCLK =
8 MHz 16 MHz 24 MHz 32 MHz 40 MHz 48 MHz
PARAMETER V
CC
UNIT
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
2.2 V
I
LPM0_DCDC_VCORE0
µA
3.0 V 500 950
2.2 V
I
LPM0_DCDC_VCORE1
µA
3.0 V 800 1350
(1) MCLK sourced by DCO.
(2) Current measured into V
CC
.
(3) All other input pins tied to 0 V or V
CC
. Outputs do not source or sync any current.
(4) CPU is OFF, Flash or SRAM not being accessed.
(5) All SRAM banks kept active.
(6) All peripherals are inactive.
20 Specifications Copyright © 2015, Texas Instruments Incorporated
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