Datasheet

PRODUCTPREVIEW
MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
5.9 Current Consumption
Table 5-1. Current Consumption During Device Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)(2)(3)
PARAMETER V
CC
TYP MAX UNIT
2.2 V
I
RESET
µA
3.0 V 540 1300
(1) Device held in reset through RSTn/NMI pin.
(2) Current measured into V
CC
.
(3) All other input pins tied to 0 V or V
CC
. Outputs do not source or sync any current.
Table 5-2. Current Consumption in LDO-Based Active Modes
over recommended operating free-air temperature (unless otherwise noted)
(1)(2)(3)(4)(5)
MCLK = MCLK = MCLK = MCLK = MCLK = MCLK =
EXECUTION
8 MHz 16 MHz 24 MHz 32 MHz 40 MHz 48 MHz
PARAMETER V
CC
UNIT
MEMORY
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
I
AM_LDO_VCORE0,Flash
(6) (7)
Flash 3.0 V 3950 4700 µA
I
AM_LDO_VCORE1,Flash
(6) (7)
Flash 3.0 V 7600 8500 µA
I
AM_LDO_VCORE0,SRAM
(8)
SRAM 3.0 V µA
I
AM_LDO_VCORE1,SRAM
(8)
SRAM 3.0 V µA
(1) MCLK sourced by DCO.
(2) Current measured into V
CC
.
(3) All other input pins tied to 0 V or V
CC
. Outputs do not source or sync any current.
(4) All SRAM banks kept active.
(5) All peripherals are inactive.
(6) Device executing the Dhrystone 2.1 algorithm. Code execution from Flash, stack and data in SRAM.
(7) Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
(8) Device executing the Dhrystone 2.1 algorithm. Code execution from SRAM, stack and data in SRAM.
Table 5-3. Current Consumption in DC-DC-Based Active Modes
over recommended operating free-air temperature (unless otherwise noted)
(1)(2)(3)(4)(5)
MCLK = MCLK = MCLK = MCLK = MCLK = MCLK =
EXECUTION
8 MHz 16 MHz 24 MHz 32 MHz 40 MHz 48 MHz
PARAMETER V
CC
UNIT
MEMORY
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
I
AM_DCDC_VCORE0,Flash
(6) (7)
Flash 3.0 V 2200 2800 µA
I
AM_DCDC_VCORE1,Flash
(6) (7)
Flash 3.0 V 4600 5400 µA
I
AM_DCDC_VCORE0,SRAM
(8)
SRAM 3.0 V µA
I
AM_DCDC_VCORE1,SRAM
(8)
SRAM 3.0 V µA
(1) MCLK sourced by DCO.
(2) Current measured into V
CC
.
(3) All other input pins tied to 0 V or V
CC
. Outputs do not source or sync any current.
(4) All SRAM banks kept active.
(5) All peripherals are inactive.
(6) Device executing the Dhrystone 2.1 algorithm. Code execution from Flash, stack and data in SRAM.
(7) Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
(8) Device executing the Dhrystone 2.1 algorithm. Code execution from SRAM, stack and data in SRAM.
Copyright © 2015, Texas Instruments Incorporated Specifications 19
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M