Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
5.8 Operating Mode Execution Frequency vs Flash Wait-State Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAXIMUM SUPPORTED MCLK FREQUENCY
(1)
,
(2)
NUMBER OF
FLASH READ
PARAMETER FLASH WAIT UNIT
AM_LDO_VCORE0, AM_LDO_VCORE1,
MODE
STATES
AM_DCDC_VCORE0 AM_DCDC_VCORE1
Normal read
f
MAX_NRM_FLWAIT0
0 12 16 MHz
mode
Normal read
f
MAX_NRM_FLWAIT1
1 24 32 MHz
mode
Normal read
f
MAX_NRM_FLWAIT2
2 24 48 MHz
mode
Other read
f
MAX_ORM_FLWAIT0
0 6 8 MHz
modes
(3)
Other read
f
MAX_ORM_FLWAIT1
1 12 16 MHz
modes
(3)
Other read
f
MAX_ORM_FLWAIT2
2 18 24 MHz
modes
(3)
Other read
f
MAX_ORM_FLWAIT3
3 24 32 MHz
modes
(3)
Other read
f
MAX_ORM_FLWAIT4
4 24 40 MHz
modes
(3)
Other read
f
MAX_ORM_FLWAIT5
5 24 48 MHz
modes
(3)
(1) Violation of the maximum frequency limitation for a given wait-state configuration results in nondeterministic data or instruction fetches
from the flash memory.
(2) In low-frequency active modes, the flash can always be accessed in zero wait-state because the maximum MCLK frequency is limited to
128 kHz.
(3) Other read modes refer to Read Margin 0/1, Read Margin 0B/1B, Program Verify, Erase Verify, and Leakage Verify.
18 Specifications Copyright © 2015, Texas Instruments Incorporated
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