Datasheet

PRODUCTPREVIEW
MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
5.4 Recommended External Components
(1) (2) (3)
MIN TYP MAX UNIT
For DC-DC operation
(4)
3.3 4.7
C
DVCC
Capacitor on DVCC pin µF
For LDO-only operation 3.3 4.7
For DC-DC operation, including
1.54 4.7 9 µF
capacitor tolerance
C
VCORE
Capacitor on VCORE pin
For LDO-only operation, including
70 100 9000 nF
capacitor tolerance
C
AVCC
Capacitor on AVCC pin 3.3 4.7 µF
L
VSW
Inductor between VSW and VCORE pins for DC-DC 3.3 4.7 13 µH
R
LVSW-DCR
Allowed DCR for L
VSW
150 350 mΩ
I
SAT-LVSW
L
VSW
saturation current 700 mA
(1) For optimum performance, select the component value to match the typical value given in the table.
(2) Refer to the section on board guidelines for further details on component selection, placement as well as related PCB design guidelines.
(3) Tolerance of the capacitance/inductance values should be taken into account when choosing a component, in order to ensure that the
Min/Max ranges are never exceeded
(4) C
DVCC
should not be smaller than C
VCORE
5.5 Operating Mode V
CC
Ranges
over operating free-air temperature (unless otherwise noted)
PARAMETER OPERATING MODE TEST CONDITIONS MIN MAX UNIT
AM_LDO_VCORE0
(1)(2)
LDO active, SVSMH enabled, Flash not
1.62 3.7
AM_LF_VCORE0 active
LPM0_LDO_VCORE0
LDO active, SVSMH enabled, Flash active 1.71 3.7
V
CC_LDO_VCORE0
LPM0_LF_VCORE0 V
LPM3_VCORE0
LDO active, SVSMH disabled, Flash active 1.62 3.7
LPM4_VCORE0
LPM3.5
AM_LDO_VCORE1
(1)(2)
LDO active, SVSMH enabled, Flash active 1.71 3.7
AM_LF_VCORE1
LPM0_LDO_VCORE1
V
CC_LDO_VCORE1
V
LPM0_LF_VCORE1
LDO active, SVSMH disabled, Flash active 1.62 3.7
LPM3_VCORE1
LPM4_VCORE1
AM_DCDC_VCORE0
(3)(4)
V
CC_DCDC_VCORE0
DC-DC active, SVSMH enabled or disabled 2.18 3.7 V
LPM0_DCDC_VCORE0
AM_DCDC_VCORE1
(3)(4)
V
CC_DCDC_VCORE1
DC-DC active, SVSMH enabled or disabled 2.18 3.7 V
LPM0_DCDC_VCORE1
V
CC_VCORE_OFF
LPM4.5
(5)
LDO disabled, SVSMH enabled or disabled 1.62 3.7 V
(1) LPM0 mode associated with each active mode will have a similar V
CC
range restriction.
(2) Flash remains active only in active modes and LPM0 modes.
(3) Low frequency active, Low frequency LPM0, LPM3, LPM4, and LPM3.5 modes are based on LDO only.
(4) When V
CC
falls below the specified Min value, the DC-DC operation will switch to LDO automatically, as long as the V
CC
drop is slower
than the rate that is reliably detected. Refer to <ref> for more details.
(5) Core voltage is switched off in LPM4.5 mode.
16 Specifications Copyright © 2015, Texas Instruments Incorporated
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