Datasheet

PRODUCTPREVIEW
MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
6.10.22 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
Table 6-53. Port PJ (PJ.4 to PJ.5) Pin Functions
CONTROL BITS OR SIGNALS
(1)
SWJ MODE OF
PIN NAME (P7.x) x FUNCTION
OPERATION
(1)
PJDIR.x PJSEL1.x PJSEL0.x PJMAPx
PJ.4/TDI/ADC14CLK 4 PJ.4 (I/O) I: 0; O: 1 0 0 X X
(2)
,
TDI JTAG (4 wire)
X 0 1 default
(3)
DVcc SWD (2 wire)
ADC12CLK 1 1 0 X X
DVcc X 1 1 X X
PJ.5/TDO/SWO
(4)
, 5 PJ.5 (I/O) I: 0; O: 1 0 0 X X
(5)
TDO JTAG (4 wire)
X 0 1 default
(3)
SWO SWD (2 wire)
Hi-Z X 1 X X X
(1) X indicates that the value of the control signal or mode of operation has no effect on the functionality.
(2) This pin is internally pulled up if PJSEL0 is 1.
(3) The 'default' value in the table indicates the functionality that is selected whenever a Hard Reset (or higher class reset) occurs.
(4) This pin is has NO internal pull feature. If used in User IO mode or left unused, it must be pulled to GND through an external pulldown
resistor.
(5) After any Hard Reset (or higher class reset), this pin returns to TDO functionality with the SWJ in JTAG (4 wire) mode of operation. If
used as a User IO, it reflects the value of the external pullup until the PJSELx bits are reconfigured to the value 00.
Copyright © 2015, Texas Instruments Incorporated Detailed Description 137
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M