Datasheet

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MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
Table 6-52. Port PJ (PJ.2 and PJ.3) Pin Functions
CONTROL BITS OR SIGNALS
(1)
PIN NAME (PJ.x) x FUNCTION
HFXT
PJDIR.x PJSEL1.2 PJSEL0.2 PJSEL1.3 PJSEL0.3
BYPASS
PJ.3/HFXIN 3 PJ.3 (I/O) I: 0; O: 1 X X 0 0 X
N/A 0
X X 1 X X
DVSS 1
HFXIN crystal mode
(2)
X X X 0 1 0
HFXIN bypass mode
(2)
X X X 0 1 1
PJ.2/HFXOUT 2 0 0
0
PJ.2 (I/O) I: 0; O: 1 0 0 1 X
X X 1
(3)
0 0
0
N/A 0 see
(4)
see
(4)
1 X
X X 1
(3)
0 0
0
DVSS 1 see
(4)
see
(4)
1 X
X X 1
(3)
HFXOUT crystal mode
(2)
X X X 0 1 0
(1) X = Don't care
(2) Setting PJSEL1.3 = 0 and PJSEL0.3 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.2 and PJ.3 are
configured for crystal operation and PJSEL1.2 and PJSEL0.2 are do not care. When HFXTBYPASS = 1, PJ.3 is configured for bypass
operation and PJ.2 is configured as general-purpose I/O.
(3) When PJ.3 is configured in bypass mode, PJ.2 is configured as general-purpose I/O.
(4) With PJSEL0.2 = 1 or PJSEL1.2 =1 the general-purpose I/O functionality is disabled. No input function is available. When configured as
output, the pin is actively pulled to zero.
136 Detailed Description Copyright © 2015, Texas Instruments Incorporated
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