Datasheet

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MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
Table 6-51. Port PJ (PJ.0 and PJ.1) Pin Functions
CONTROL BITS OR SIGNALS
(1)
PIN NAME (PJ.x) x FUNCTION
LFXT
PJDIR.x PJSEL1.1 PJSEL0.1 PJSEL1.0 PJSEL0.0
BYPASS
PJ.0/LFXIN 0 PJ.0 (I/O) I: 0; O: 1 X X 0 0 X
N/A 0
X X 1 X X
DVSS 1
LFXIN crystal mode
(2)
X X X 0 1 0
LFXIN bypass mode
(2)
X X X 0 1 1
PJ.1/LFXOUT 1 0 0
0
PJ.1 (I/O) I: 0; O: 1 0 0 1 X
X X 1
(3)
0 0
0
N/A 0 see
(4)
see
(4)
1 X
X X 1
(3)
0 0
0
DVSS 1 see
(4)
see
(4)
1 X
X X 1
(3)
LFXOUT crystal mode
(2)
X X X 0 1 0
(1) X = Don't care
(2) Setting PJSEL1.0 = 0 and PJSEL0.0 = 1 causes the general-purpose I/O to be disabled. When LFXTBYPASS = 0, PJ.0 and PJ.1 are
configured for crystal operation and PJSEL1.1 and PJSEL0.1 are do not care. When LFXTBYPASS = 1, PJ.0 is configured for bypass
operation and PJ.1 is configured as general-purpose I/O.
(3) When PJ.0 is configured in bypass mode, PJ.1 is configured as general-purpose I/O.
(4) With PJSEL0.1 = 1 or PJSEL1.1 =1 the general-purpose I/O functionality is disabled. No input function is available. When configured as
output, the pin is actively pulled to zero.
Copyright © 2015, Texas Instruments Incorporated Detailed Description 133
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