Datasheet

PRODUCTPREVIEW
PJ.0/LFXIN
PJSEL0.0
PJDIR.0
PJIN.0
EN
To modules
DVSS
PJOUT.0
1
0
DVSS
DVCC
1
D
To LFXT XIN
Pad Logic
Bus
Keeper
Direction
0: Input
1: Output
PJREN.0
0 1
0 0
1 0
1 1
PJSEL1.0
0 1
0 0
1 0
1 1
DVSS
DVSS
MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
6.10.20 Port PJ, PJ.0 and PJ.1 Input/Output With Schmitt Trigger
Functional representation only.
Copyright © 2015, Texas Instruments Incorporated Detailed Description 131
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