Datasheet

PRODUCTPREVIEW
Py.x/USCI/Mod/Cp.q
PySEL1.x
PyDIR.x
PyIN.x
EN
To modules
From USCI
PyOUT.x
1
0
DVSS
DVCC
1
D
To Comparator
From Comparator
Pad Logic
Bus
Keeper
Direction
0: Input
1: Output
CPD.q
PyREN.x
0 1
0 0
1 0
1 1
PySEL0.x
0 1
0 0
1 0
1 1
From module
DVSS
From USCI
MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
6.10.17 Port P8, P8.0 and P8.1, Input/Output With Schmitt Trigger
Functional representation only.
Figure 6-23. Py.x/USCI/Mod/Cp.q Pin Schematic
Copyright © 2015, Texas Instruments Incorporated Detailed Description 125
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M