Datasheet

PRODUCTPREVIEW
Py.x/Mod/VREF/VeREF/Cp.q
PySEL1.x
PyDIR.x
PyIN.x
EN
To module
From module
PyOUT.x
1
0
DVSS
DVCC
1
D
To Comparator
From Comparator
Pad Logic
Bus
Keeper
Direction
0: Input
1: Output
CPD.q
PyREN.x
0 1
0 0
1 0
1 1
PySEL0.x
0 1
0 0
1 0
1 1
DVSS
DVSS
ADC Reference
MSP432P401R, MSP432P401M
www.ti.com SLAS826 –MARCH 2015
6.10.14 Port P5, P5.6 and P5.7, Input/Output With Schmitt Trigger
Functional representation only.
Figure 6-20. Py.x/Mod/VREF/VeREF/Cp.q Pin Schematic
Copyright © 2015, Texas Instruments Incorporated Detailed Description 119
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