Datasheet

PRODUCTPREVIEW
PySEL1.x
PyDIR.x
PyIN.x
EN
To modules
From module 1
†
PyOUT.x
1
0
DVSS
DVCC
1
D
Pad Logic
To ADC
From ADC
Bus
Keeper
Direction
0: Input
1: Output
PyREN.x
0 1
0 0
1 0
1 1
PySEL0.x
0 1
0 0
1 0
1 1
DVSS
Py.x/Mod1/Mod2/Az
From module 2
†
†
Output will be DVSS if module 1 or module 2 function is not available. Refer to pin function tables.
MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
6.10.9 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
Functional representation only.
Figure 6-19. Py.x/Mod1/Mod2/Az Pin Schematic
112 Detailed Description Copyright © 2015, Texas Instruments Incorporated
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