Datasheet

PRODUCTPREVIEW
Py.x/Mod1/Mod2
PySEL1.x
PyDIR.x
PyIN.x
EN
To module
From module
PyOUT.x
1
0
DVSS
DVCC
1
D
Pad Logic
Direction
0: Input
1: Output
PyREN.x
0 1
0 0
1 0
1 1
PySEL0.x
0 1
0 0
1 0
1 1
DVSS
DVSS
MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
6.10.6 Port P2, P2.4 to P2.7, Input/Output With Schmitt Trigger
Functional representation only.
Figure 6-18. Py.x/Mod1/Mod2 Pin Schematic
108 Detailed Description Copyright © 2015, Texas Instruments Incorporated
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