Datasheet

PRODUCTPREVIEW
MSP432P401R, MSP432P401M
SLAS826 –MARCH 2015 www.ti.com
4.2 Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Signal Descriptions
TERMINAL
NO.
(2)
I/O
(1)
DESCRIPTION
NAME
PZ ZXH RGC
General-purpose digital I/O
P10.1/
1 N/A N/A I/O Clock signal input – eUSCI_B3 SPI slave mode
UCB3CLK
Clock signal output – eUSCI_B3 SPI master mode
General-purpose digital I/O
P10.2/
2 N/A N/A I/O Slave in, master out – eUSCI_B3 SPI mode
UCB3SIMO/UCB3SDA
I
2
C data – eUSCI_B3 I
2
C mode
General-purpose digital I/O
P10.3/
3 N/A N/A I/O Slave out, master in – eUSCI_B3 SPI mode
UCB3SOMI/UCB3SCL
I
2
C clock – eUSCI_B3 I
2
C mode
General-purpose digital I/O with port interrupt, wake-up and glitch filtering
P1.0/
4 A1 1 I/O capability
UCA0STE
Slave transmit enable – eUSCI_A0 SPI mode
General-purpose digital I/O with port interrupt and wake-up capability
P1.1/
5 B1 2 I/O Clock signal input – eUSCI_A0 SPI slave mode
UCA0CLK
Clock signal output – eUSCI_Ao0 SPI master mode
General-purpose digital I/O with port interrupt and wake-up capability
P1.2/
6 C4 3 I/O Receive data – eUSCI_A0 UART mode
UCA0RXD/UCA0SOMI
Slave out, master in – eUSCI_A0 SPI mode
General-purpose digital I/O with port interrupt and wake-up capability
P1.3/
7 D4 4 I/O Transmit data – eUSCI_A0 UART mode
UCA0TXD/UCA0SIMO
Slave in, master out – eUSCI_A0 SPI mode
General-purpose digital I/O with port interrupt, wake-up and glitch filtering
P1.4/
8 D3 5 I/O capability
UCB0STE
Slave transmit enable – eUSCI_B0 SPI mode
General-purpose digital I/O with port interrupt, wake-up and glitch filtering
P1.5/ capability
9 C1 6 I/O
UCB0CLK Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
General-purpose digital I/O with port interrupt and wake-up capability
P1.6/
10 D1 7 I/O Slave in, master out – eUSCI_B0 SPI mode
UCB0SIMO/UCB0SDA
I
2
C data – eUSCI_B0 I
2
C mode
General-purpose digital I/O with port interrupt and wake-up capability
P1.7/
11 E1 8 I/O Slave out, master in – eUSCI_B0 SPI mode
UCB0SOMI/UCB0SCL
I
2
C clock – eUSCI_B0 I
2
C mode
Regulated core power supply (internal use only, no external current
VCORE
(3)
12 C2 9
loading)
DVCC1 13 D2 10 Digital power supply
VSW 14 E2 11 DC-to-DC converter switching output.
DVSS1 15 F2 12 Digital ground supply
P2.0/ General-purpose digital I/O with port interrupt and wake-up capability
16 E4 13 I/O
PM_UCA1STE Slave transmit enable – eUSCI_A1 SPI mode
General-purpose digital I/O with port interrupt and wake-up capability
P2.1/
17 F1 14 I/O Clock signal input – eUSCI_A1 SPI slave mode
PM_UCA1CLK
Clock signal output – eUSCI_A1 SPI master mode
P2.2/ General-purpose digital I/O with port interrupt and wake-up capability
PM_UCA1RXD/ 18 E3 15 I/O Receive data – eUSCI_A1 UART mode
PM_UCA1SOMI Slave out, master in – eUSCI_A1 SPI mode
(1) I = input, O = output
(2) N/A = not available
(3) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C
VCORE
.
10 Terminal Configuration and Functions Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M