Product Folder Sample & Buy Technical Documents Tools & Software Support & Community MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 MSP432P401x Mixed-Signal Microcontrollers 1 Device Overview 1.1 Features • Core – ARM® 32-Bit Cortex®-M4F CPU With Floating Point Unit and Memory Protection Unit – Frequency up to 48 MHz – Performance Benchmark: • 1.196 DMIPS/MHz (Dhrystone 2.1) • 3.41 CoreMark/MHz – Energy Benchmark: • 153.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 1.2 • • www.ti.com Applications Industrial and Automation – Home Automation – Smoke Detectors – Barcode Scanners Metering – Electric Meters – Flow Meters 1.3 • • Health and Fitness – Watches – Activity Monitors – Fitness Accessories – Blood Glucose Meters Consumer Electronics – Mobile Devices – Sensor Hubs Description The MSP432P401x device family is TI's latest addition to its portfolio of efficient ultra-low-power mixedsignal MCUs.
MSP432P401R, MSP432P401M www.ti.com 1.4 SLAS826 – MARCH 2015 Functional Block Diagram Figure 1-1 shows the functional block diagram of the MSP432P401x devices. LFXIN, LFXOUT, HFXIN HFXOUT DCOR P1.x to P10.x PJ.x LPM3.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table of Contents 1 2 3 4 5 Device Overview ......................................... 1 6.2 Memory Map 1.1 Features .............................................. 1 6.3 Memories on the MSP432P401x .................... 66 1.2 Applications ........................................... 2 6.4 DMA ................................................. 75 1.3 Description ............................................ 2 6.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 3 Device Comparison Table 3-1 lists the features of the MSP432P401x devices. Table 3-1.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagrams Figure 4-1 shows the pinout of the 100-pin PZ package.
MSP432P401R, MSP432P401M P6.2/UCB1STE/C1.5 P6.3/UCB1CLK/C1.4 P6.4/UCB1SIMO/UCB1SDA/C1.3 P6.5/UCB1SOMI/UCB1SCL/C1.2 P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1 P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0 DVSS3 RSTn/NMI AVSS2 PJ.2/HFXOUT PJ.3/HFXIN AVCC2 P7.0/PM_SMCLK/PM_DMAE0 P7.1/PM_C0OUT/PM_TA0CLK P7.2/PM_C1OUT/PM_TA1CLK P7.3/PM_TA0.0 PJ.4/TDI/ADC14CLK PJ.5/TDO/SWO SWDIOTMS SWCLKTCK P9.4/UCA3STE P9.5/UCA3CLK P9.6/UCA3RXD/UCA3SOMI P9.7/UCA3TXD/UCA3SIMO SLAS826 – MARCH 2015 P10.0/UCB3STE www.ti.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Figure 4-2 shows the pinout of the 80-pin ZXH package. P1.0 SWCLKTCK PJ.5 A1 A2 A3 P1.1 SWDIOTMS PJ.4 B1 B2 B3 P1.5 VCORE P7.3 PJ.3 PJ.2 P6.5 P6.4 P6.2 A4 A5 A6 A7 A8 A9 P6.6 P6.3 B8 B9 P7.2 B4 P1.2 P5.3 P5.4 P5.6 D7 D8 D9 P5.0 P5.1 P5.2 E7 E8 E9 P1.4 D2 D3 D4 P1.7 VSW P2.2 P2.0 E1 E2 E3 E4 P2.6 C5 C6 P5.7 D5 DVCC1 D1 P2.5 P7.1 DVCC2 DVSS3 P5.5 P1.3 AVCC2 AVSS2 P1.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1 P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0 DVSS3 RSTn/NMI AVSS2 PJ.2/HFXOUT PJ.3/HFXIN AVCC2 P7.0/PM_SMCLK/PM_DMAE0 P7.1/PM_C0OUT/PM_TA0CLK P7.2/PM_C1OUT/PM_TA1CLK P7.3/PM_TA0.0 PJ.4/TDI/ADC14CLK PJ.5/TDO/SWO SWDIOTMS SWCLKTCK Figure 4-3 shows the pinout of the 64-pin RGC package. 1 48 DVCC2 P1.1/UCA0CLK 2 47 DVSS2 P1.2/UCA0RXD/UCA0SOMI 3 46 P5.7/TA2.2/VREF-/VeREF-/C1.6 P1.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 4.2 www.ti.com Signal Descriptions Table 4-1 describes the signals for all device variants and package options. Table 4-1. Signal Descriptions TERMINAL NAME NO. (2) I/O (1) DESCRIPTION PRODUCT PREVIEW PZ ZXH RGC P10.1/ UCB3CLK 1 N/A N/A I/O General-purpose digital I/O Clock signal input – eUSCI_B3 SPI slave mode Clock signal output – eUSCI_B3 SPI master mode P10.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 4-1. Signal Descriptions (continued) TERMINAL NO. (2) I/O (1) DESCRIPTION PZ ZXH RGC P2.3/ PM_UCA1TXD/ PM_UCA1SIMO 19 F4 16 I/O General-purpose digital I/O with port interrupt and wake-up capability Transmit data – eUSCI_A1 UART mode Slave in, master out – eUSCI_A1 SPI mode P2.4/ PM_TA0.1 20 F3 N/A I/O General-purpose digital I/O with port interrupt and wake-up capability TA0 CCR1 capture: CCI1A input, compare: Out1 P2.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME NO. (2) I/O (1) DESCRIPTION PRODUCT PREVIEW PZ ZXH RGC P3.6/ PM_UCB2SIMO/ PM_UCB2SDA 38 J5 25 I/O General-purpose digital I/O with port interrupt and wake-up capability Slave in, master out – eUSCI_B2 SPI mode I2C data – eUSCI_B2 I2C mode P3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 4-1. Signal Descriptions (continued) TERMINAL NO. (2) I/O (1) DESCRIPTION PZ ZXH RGC P4.6/ A7 62 F8 37 I/O General-purpose digital I/O with port interrupt and wake-up capability ADC analog input A7 P4.7/ A6 63 F9 38 I/O General-purpose digital I/O with port interrupt and wake-up capability ADC analog input A6 P5.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME NO. (2) PZ ZXH I/O (1) DESCRIPTION RGC General-purpose digital I/O with port interrupt, wake-up and glitch filtering capability TA2 CCR4 capture: CCI4A input, compare: Out4 Slave out, master in – eUSCI_B3 SPI mode I2C clock – eUSCI_B3 I2C mode Comparator_E1 input 0 PRODUCT PREVIEW P6.7/ TA2.4/ UCB3SOMI/UCB3SCL/ C1.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 5 Specifications 5.1 Absolute Maximum Ratings (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Voltage applied at DVCC and AVCC pins to VSS Voltage difference between DVCC and AVCC pins Voltage applied to any pin MIN MAX UNIT –0.3 4.17 V ±0.3 V –0.3 VCC + 0.3 V (4.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Recommended External Components (1) 5.4 CDVCC Capacitor on DVCC pin CVCORE (2) (3) MIN TYP For DC-DC operation (4) 3.3 4.7 For LDO-only operation 3.3 4.7 1.54 4.7 9 µF 70 100 9000 nF For DC-DC operation, including capacitor tolerance Capacitor on VCORE pin For LDO-only operation, including capacitor tolerance MAX UNIT µF CAVCC Capacitor on AVCC pin 3.3 4.7 LVSW Inductor between VSW and VCORE pins for DC-DC 3.3 4.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Operating Mode CPU Frequency Ranges (1) 5.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 5.8 www.ti.
MSP432P401R, MSP432P401M www.ti.com 5.9 SLAS826 – MARCH 2015 Current Consumption Table 5-1. Current Consumption During Device Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TYP MAX 540 1300 UNIT 2.2 V IRESET (1) (2) (3) (1) (2) (3) 3.0 V µA Device held in reset through RSTn/NMI pin. Current measured into VCC. All other input pins tied to 0 V or VCC. Outputs do not source or sync any current. Table 5-2.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-4. Current Consumption in Low-Frequency Active Modes over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) (3) (4) (5) PARAMETER IAM_LF_VCORE0, Flash IAM_LF_VCORE1, Flash IAM_LF_VCORE0, SRAM IAM_LF_VCORE1, SRAM (1) (2) (3) (4) (5) (6) (7) (8) EXECUTION MEMORY (6) (7) (8) (8) TYP 25°C MAX TYP 60°C MAX TYP 85°C MAX TYP MAX 2.2 V Flash (6) (7) –40°C VCC 3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 5-7. Current Consumption in Low-Frequency LPM0 Modes over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) (3) (4) (5) (6) PARAMETER VCC 25°C MAX TYP 60°C MAX TYP 85°C MAX TYP MAX 2.2 V ILPM0_LF_VCORE0 3.0 V 70 530 70 625 2.2 V ILPM0_LF_VCORE1 (1) (2) (3) (4) (5) (6) –40°C TYP 3.0 V UNIT μA μA Current measured into VCC. All other input pins tied to 0 V or VCC.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-9. Current Consumption in LPM3.5, LPM4.5 Modes over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER VCC 25°C MAX TYP 60°C MAX TYP 85°C MAX TYP MAX 2.2 V ILPM3.5_RTCLF (3) (4) (5) (6) (7) 3.0 V 0.8 17 1.3 18 0.1 7 2.2 V ILPM3.5_RTCREFO (3) (4) (8) (6) (7) 3.0 V 2.2 V ILPM4.5 (9) (10) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) –40°C TYP 3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 5.10 Timing and Switching Characteristics 5.10.1 Mode Transition Timing Table 5-11. Active Mode Transition Latencies over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) FINAL OPERATING MODE TEST CONDITIONS tOFF_AMLDO0,100 nF Power Off AM_LDO_VCORE0 tOFF_AMLDO0,4.7 µF Power Off tAMLDO0_AMLDO1 LATENCY UNIT TYP MAX From VCC reaching 1.65 V to start of application code. CVCORE = 100 nF. 4.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-12.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 5-13.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-14. LPM3.5, LPM4.5 Mode Transition Latencies over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ORIGINAL OPERATING MODE FINAL OPERATING MODE (1) AM_LDO_VCORE0 LPM3.5 AM_DCDC_VCORE0 tAMLDO0_LPM3.5 tAMDCDC0_LPM3.5 tAMLF0_LPM3.5 (1) tAMLDO1_LPM3.5 (1) tAMDCDC1_LPM3.5 tAMLF1_LPM3.5 (2) tAMDCDC0_LPM4.5 (2) (2) PRODUCT PREVIEW tAMLDO1_LPM4.5 (2) tAMDCDC1_LPM4.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 5.10.2 Reset Timing Table 5-15.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 5-18. Low-Frequency Crystal Oscillator, LFXT over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) IVCC,LFXT fLFXT Current consumption (1) LFXT oscillator crystal frequency TEST CONDITIONS VCC fOSC = 32.768 kHz LFXTBYPASS = 0, LFXTDRIVE = {0}, CL,eff = 3.7 pF Typical ESR, CSHUNT 3.0 V 100 fOSC = 32.768 kHz LFXTBYPASS = 0, LFXTDRIVE = {1}, CL,eff = 6 pF Typical ESR, CSHUNT 3.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-19.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 5-20.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 High-Frequency Crystal Oscillator, HFXT (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS tSTART,HFXT Start-up time (4) CL,eff fFault,HFXT (4) (5) (6) (7) (8) VCC MIN 3.57 fOSC = 4 MHz HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 0 CL,eff = 16 pF Typical ESR , CSHUNT FCNTHF_EN = 0 0.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-21. DCO over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fRSEL0_CTR fRSEL1_CTR fRSEL2_CTR fRSEL3_CTR PRODUCT PREVIEW fRSEL4_CTR fRSEL5_CTR dfDCO/dT (1) TEST CONDITIONS VCC , TA MIN TYP MAX DCO frequency center range 0 initial accuracy , with trimmed factory settings Internal resistor option DCORSEL = 0, DCOTUNE = 0 3.0 V 25°C 1.4925 1.5 1.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 DCO (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC , TA MIN TYP MAX UNIT DCO settling from worst case DCORSELn to DCORSELm DCO settled to within 0.5% of steady state frequency See Figure 5-1. 1.62 V to 3.7 V –40°C to 85°C 5 μs DCO settling LSB change of DCOTUNE within any DCORSEL setting DCO settled to within 0.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-23. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Current consumption (1) IVLO VCC fVLO VLO frequency (2) dfVLO/dT VLO frequency temperature drift (3) (2) 1.62 V to 3.7 V (2) 1.62 V to 3.7 V dfVLO/dVCC VLO frequency supply voltage drift (4) DCVLO (1) (2) (3) (4) MIN TYP 1.62 V to 3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 5-26. System Oscillator (SYSOSC) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT ISYSOSC Current consumption (1) 1.62 V to 3.7 V fSYSOSC SYSOSC frequency 1.62 V to 3.7 V dfSYSOSC/ dT SYSOSC frequency temperature drift (2) 1.62 V to 3.7 V 0.03 %/℃ dfSYSOSC/ dVCC SYSOSC frequency supply voltage drift (3) 1.62 V to 3.7 V 0.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 5.10.4 Voltage Regulators Table 5-28. VCORE Regulator (LDO) Characteristics PARAMETER PRODUCT PREVIEW MIN TYP MAX UNIT VCORE0-HP Static VCORE voltage Level 0 in active and LPM0 modes Device power modes AM_LDO_VCORE0, LPM0_LDO_VCORE0 1.07 1.2 1.27 V VCORE1-HP Static VCORE voltage Level 1 in active and LPM0 modes Device power modes AM_LDO_VCORE1, LPM0_LDO_VCORE1 1.25 1.4 1.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 5-30. PSS, VCCDET over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER MIN TYP MAX UNIT VVCC_VCCDET- VCCDET power-down level | dDVCC/dt | < 3 V/s (1) - trip point with falling VCC 0.64 1.1 1.62 V VVCC_VCCDET+ VCCDET power-up level trip point with rising VCC 0.70 1.165 1.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com PSS, SVSMH (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VSVSMH-,LP VSVSMH_hys PRODUCT PREVIEW tPD,SVSMH t(SVSMH) (1) 40 SVSMH threshold level; Low Power Mode [falling DVCC] TEST CONDITIONS MIN TYP MAX SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 0, DC (dDVCC/dt < 1V/s) trimmed 1.47 1.54 1.62 SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 1, DC (dDVCC/dt < 1V/s) trimmed 1.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 5-32.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 5.10.5 Digital I/Os Table 5-33. Digital Inputs (Applies to Both Normal and High-Drive I/Os) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX 2.2 V 0.99 1.65 3V 1.35 2.25 2.2 V 0.55 1.21 3V 0.75 1.65 2.2 V 0.32 0.84 3V 0.4 1.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 5-34. Digital Outputs, Normal I/Os over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS VCC I(OHmax) = –1 mA (1) VOH 2.2 V I(OHmax) = –3 mA (2) High-level output voltage I(OHmax) = –2 mA (1) 3.0 V I(OHmax) = –6 mA (2) I(OLmax) = 1 mA (1) VOL 2.2 V I(OLmax) = 3 mA (2) Low-level output voltage I(OLmax) = 2 mA (1) 3.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-35. Digital Outputs, High-Drive I/Os over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC I(OHmax) = –5 mA (1) VOH 2.2 V I(OHmax) = –15 mA (2) High-level output voltage I(OHmax) = –10 mA (1) 3.0 V I(OHmax) = –20 mA (2) I(OLmax) = 5 mA (1) VOL 2.2 V I(OLmax) = 15 mA (2) Low-level output voltage I(OLmax) = 10 mA (1) 3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 5.10.6 14-Bit ADC Table 5-37. 14-Bit ADC, Power Supply and Input Range Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS VCC MIN NOM MAX UNIT Analog supply voltage AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V, ADC14PWRMD = 2 1.62 3.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-38. 14-Bit ADC, Timing Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fADC14CLK TEST CONDITIONS For specified performance of ADC14 linearity parameters TYP 25 200 ksps, ADC14PWRMD = 2 1.62 V to 3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 5-40.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-42. 14-Bit ADC, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VeREF+ Positive external reference voltage input VeREF+ > VeREF- (1) 1.45 AVCC V VeREF- Negative external reference voltage VeREF+ > VeREFinput (2) 0 AVCC – 1.45 V (VeREF+ VeREF-) Differential external reference voltage input (3) 1.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 5.10.7 REF_A Table 5-43. REF_A, Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS Positive built-in reference voltage output VREF+ VCC MIN TYP MAX REFVSEL = {0} for 1.2 V REFON = 1 1.62 V 1.2 ±1% REFVSEL = {1} for 1.45 V REFON = 1 1.75 V 1.45 ±1% REFVSEL = {2} for 2.0 V REFON = 1 2.3 V 2.0 ±1% REFVSEL = {3} for 2.5 V REFON = 1 2.8 V 2.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 5.10.8 Comparator_E Table 5-44. Comparator_E over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS Supply voltage IAVCC_COMP IAVCC_REF Comparator operating supply current into AVCC, Excludes reference resistor ladder Quiescent current of resistor ladder into AVCC, Includes REF_A module current PRODUCT PREVIEW Reference voltage level VREF 1.62 50 3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Comparator_E (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) tEN_CMP tEN_CMP_VREF tEN_CMP_RL VCMP_REF TYP MAX CMPON = 0 to CMPON = 1, CMPPWRMD = 00, VIN+, VIN- from pins, Overdrive = 20 mV 0.6 1 Comparator enable CMPON = 0 to CMPON = 1, CMPPWRMD = 01, time VIN+, VIN- from pins, Overdrive = 20 mV 0.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 5.10.9 eUSCI Table 5-45. eUSCI (UART Mode), Recommended Operating Conditions PARAMETER feUSCI eUSCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) TEST CONDITIONS VCORE Internal: SMCLK External: UCLK Duty cycle = 50% ± 10% VCC MIN TYP MAX UNIT 1.2 V 12 1.4 V 24 1.2 V 1 1.4 V 3 MHz MHz Table 5-46.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tHD,MO tSTE,ACC tSTE,DIS tVALID,MO PRODUCT PREVIEW SIMO Figure 5-3. SPI Master Mode, CKPH = 0 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tHD,MO tSTE,ACC tVALID,MO tSTE,DIS SIMO Figure 5-4.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-49. eUSCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note (1)) PARAMETER TEST CONDITIONS VCORE VCC 1.2 V 1.62 V MIN 65 1.4 V 3.7 V 45 1.2 V 1.62 V 5 1.4 V 3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tHD,SI tSU,SI SIMO tHD,SO tSTE,DIS tVALID,SO SOMI Figure 5-6. SPI Slave Mode, CKPH = 1 Table 5-50. eUSCI (I2C Mode), Recommended Operating Conditions PARAMETER feUSCI eUSCI input clock frequency fSCL SCL clock frequency TEST CONDITIONS Internal: SMCLK External: UCLK Duty cycle = 50% ± 10% VCORE VCC MIN TYP MAX UNIT 1.2 V 12 1.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 5-51. eUSCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-7) PARAMETER TEST CONDITIONS VCC MIN fSCL = 100 kHz tHD,STA Hold time (repeated) START tSU,STA fSCL = 400 kHz Setup time for a repeated START 2.2 V, 3.0 V 500 fSCL = 100 kHz 5.0 2.2 V, 3.0 V fSCL = 1 MHz Data hold time fSCL = 400 kHz 2.2 V, 3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 5.10.10 Timer_A Table 5-52. Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Timer_A input clock frequency Internal: SMCLK External: TACLK Duty cycle = 50% ± 10% tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for capture VCC MIN TYP MAX UNIT 1.2V 12 1.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 5.10.11 Memories Table 5-53. Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS PARAMETER DVCCPGM/ERS Supply voltage for program or erase IPGM/ERS, AVG Average supply current from DVCC during program or erase IPGM/ERS, PEAK Peak supply current from DVCC during program or erase TYP 1.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 5.10.12 Emulation and Debug Table 5-55.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6 Detailed Description 6.1 Processor and Execution Features The ARM Cortex-M4 processor provides a high-performance low-cost platform that meets system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 NOTE For detailed specifications and information on the programmers model for the Cortex-M4 CPU as well as the associated peripherals mentioned throughout Section 6.1, see the appropriate reference manual at www.arm.com. 6.2 Memory Map The device supports a 4-GB address space that is divided into eight 512-MB zones (see Figure 6-1).
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com PRODUCT PREVIEW Figure 6-2. CODE Zone Memory Map 6.2.1.1 Flash Memory Region The 4-MB region from 0x0000_0000 to 0x003F_FFFF is defined as the flash memory region. This region is further divided into different types of flash memory regions which are explained in Section 6.3.1. 6.2.1.2 SRAM Memory Region The 1-MB region from 0x0100_0000 to 0x010F_FFFF is defined as the SRAM region.
MSP432P401R, MSP432P401M www.ti.com 6.2.2 SLAS826 – MARCH 2015 SRAM Zone Memory Map The SRAM Zone of the device lies in the address range of 0x2000_0000 to 0x3FFF_FFFF. This is further divided as shown in Figure 6-3. 0x3FFF_FFFF Reserved 0x2400_0000 PRODUCT PREVIEW SRAM Bit-Band Alias Region 0x2200_0000 Reserved 0x2010_0000 SRAM Memory Region 0x2000_0000 Figure 6-3. SRAM Zone Memory Map 6.2.2.1 SRAM Memory Region The 1-MB region from 0x2000_0000 to 0x200F_FFFF is defined as the SRAM region.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 0x5FFF_FFFF Reserved 0x4400_0000 Peripheral Bit-Band Alias Region 0x4200_0000 PRODUCT PREVIEW Reserved 0x4010_0000 Peripheral Region 0x4000_0000 Figure 6-4. Peripheral Zone Memory Map 6.2.3.1 Peripheral Region The 1-MB region from 0x4000_0000 to 0x400F_FFFF is dedicated to the system and application control peripherals of the device.
MSP432P401R, MSP432P401M www.ti.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 6.2.4 www.ti.com Debug and Trace Peripheral Zone This zone maps the internal as well as external PPB regions of the Cortex-M4.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 From a physical perspective the flash memory comprises of two banks, with the main and information memory regions divided equally between the two banks. This permits application to carry out a simultaneous read or execute operation from one bank while the other bank may be undergoing a program or erase operation. PRODUCT PREVIEW The memory map of flash on MSP432P401x devices is shown in Figure 6-5. Figure 6-5. Flash Memory Map 6.3.1.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.3.1.1.1 Flash Size Register (Address = 0xE004_3020h) This register reflects the size of flash main memory available on the device. Figure 6-6. SYS_FLASH_SIZE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r-1 r r 7 6 5 4 3 2 1 0 r r r r r r r r SIZE r r r r r r r r 15 14 13 12 11 10 9 8 SIZE r r r r r r r r Table 6-3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 NOTE Depending on the CPU (MCLK) frequency and the active mode in use, the flash may need to be accessed with single/multiple wait states. Whenever there is a change required in the operating frequency, it is the responsibility of the application to ensure that the flash access wait states are configured correctly before the frequency change is effected. Refer to electrical specification for details on flash wait state requirements. 6.3.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 6.3.2.1 www.ti.com SRAM Bank Enable Configuration The application can choose to optimize the power consumption of the SRAM. In order to enable this, the SRAM memory is divided into 8KB banks that can individually be powered down. Banks that are powered down remain powered down in both active as well as low-power modes of operation, thereby limiting any unnecessary inrush current when the device transitions between active and retention based low-power modes.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.3.2.3.1 SRAM Size Register (Address = 0xE004_3010h) This register reflects the size of the SRAM available on the device. Figure 6-8. SYS_SRAM_SIZE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r SIZE r r r r r r r r 15 14 13 12 11 10 9 8 SIZE r r r r r r r r Table 6-5.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-6. SYS_SRAM_BANKEN Register Description (continued) BIT FIELD TYPE RESET 7 BNK7_EN (2) RW 1h DESCRIPTION 0b = Disables Bank7 of the SRAM 1b = enables Bank7 of the SRAM When set to 1, bank enable bits for all banks below this bank are set to 1 as well. 6 BNK6_EN (2) RW 1h 0b = Disables Bank6 of the SRAM 1b = enables Bank6 of the SRAM When set to 1, bank enable bits for all banks below this bank are set to 1 as well.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 NOTE PRODUCT PREVIEW Bank0 is always enabled and cannot be disabled. In the case of all other banks, any enable/disable change will result in the SRAM_RDY bit of the SYS_SRAM_BANKEN register being set to 0 until the configuration change is effective. Any accesses to the SRAM will be stalled during this time frame, and resumed only after the SRAM banks are ready for read or write operations.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.3.2.3.3 SRAM Bank Retention Control Register (Address = E004_3018h) This register controls which bank of the SRAM is retained when the device enters LPM3 or LPM4 modes. Any bank that is not enabled for retention will be completely powered down in these modes and will lose its data Figure 6-10.
MSP432P401R, MSP432P401M www.ti.com 6.3.3 SLAS826 – MARCH 2015 ROM The MSP432P401x devices support 32KB of ROM memory, with the rest of the 1-MB region treated as reserved (for future upgrades). The lower 1KB of the ROM is reserved for TI internal purposes and accesses to this space will return an error response. The rest of the ROM is used for driver libraries. NOTE The entire ROM region returns an error response for write accesses.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-8.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 NOTE The PPB space is dedicated only to the Cortex-M4 Private Peripheral Bus. 6.5.1 Master and Slave Access Priority Settings Table 6-9 lists all the available masters (rows) and their access permissions to slaves (columns). If multiple masters can access one slave, the table lists access priorities if arbitration is required. A lower number in the table indicates a higher arbitration priority (the priority is always fixed). Table 6-9.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-10.
MSP432P401R, MSP432P401M www.ti.com 6.6.1.1 SLAS826 – MARCH 2015 NMI Control and Status Register [Address = E004_3004h] Figure 6-12. SYS_NMI_CTLSTAT Register 31 30 29 28 27 26 25 24 Reserved r r 23 22 r r r r r r 21 20 19 PIN_FLG rw-0 18 PCM_FLG r-0 17 PSS_FLG r-0 16 CS_FLG r-0 11 10 9 8 Reserved r r r r 15 14 13 12 Reserved r r 7 6 r r r r r r 5 4 r r 3 PIN_SRC rw-0 2 PCM_SRC rw-1 1 PSS_SRC rw-1 0 CS_SRC rw-1 Reserved r r Table 6-11.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-11. SYS_NMI_CTLSTAT Register Description (continued) BIT FIELD TYPE RESET 0 CS_SRC RW 1h DESCRIPTION 0b = Disables CS interrupt as a source of NMI 1b = Enables CS interrupt as a source of NMI 6.6.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 6-12. NVIC Interrupts (continued) SOURCE FLAGS IN SOURCE INTISR[31] DMA_INT3 DMA completion interrupt3 INTISR[32] DMA_INT2 DMA completion interrupt2 INTISR[33] DMA_INT1 DMA completion interrupt1 INTISR[34] DMA_INT0 (3) DMA completion interrupt0 INTISR[35] I/O Port P1 P1IFG.x (x = 0 through 7) INTISR[36] I/O Port P2 P2IFG.x (x = 0 through 7) INTISR[37] I/O Port P3 P3IFG.x (x = 0 through 7) INTISR[38] I/O Port P4 P4IFG.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 6.7 www.ti.com System Control System Control comprises the modules that govern the overall behavior of the device, including power management, operating modes, clocks, reset handling, and user configuration settings. 6.7.1 Device Resets The MSP432P401x devices support multiple classes of reset.
MSP432P401R, MSP432P401M www.ti.com 6.7.1.3 SLAS826 – MARCH 2015 Hard Reset The Hard Reset resets all modules that are set up or modified by the application. This includes all peripherals as well as the non debug logic of the Cortex-M4. The MSP432P401x devices support up to 16 sources of Hard Reset. The following table lists the reset source allocation. The Reset Controller registers can be used to identify the possible source of reset in the device.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 6.7.1.4 www.ti.com Soft Reset The Soft Reset resets only the execution component of the system, which is the non debug logic in the Cortex-M4 and the WDT_A. This reset remains nonintrusive to all other peripherals and system components. The MSP432P401x devices support up to 16 sources of Soft Reset. The following table lists the reset source allocation. The Reset Controller registers can be used to identify the possible source of reset in the design.
MSP432P401R, MSP432P401M www.ti.com 6.7.2.2 SLAS826 – MARCH 2015 Supply Supervisor and Monitor for High Side (SVSMH) The SVSMH supervises and monitors the VCC. SVSMH has a programmable threshold setting and can be used by the application to generate a reset or an interrupt if the VCC dips below the desired threshold. In supervisor mode, the SVSMH generates a device reset (POR class reset). In monitor mode, the SVSMH generates an interrupt.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 6.7.4 www.ti.com Clock System (CS) The CS contains the sources of the various clocks in the device and also controls the mapping between sources and the clock domains in the device. 6.7.4.1 LFXT The LFXT supports 32.768-kHz low-frequency crystals. 6.7.4.2 HFXT The HFXT supports high-frequency crystals up to 48 MHz. 6.7.4.3 DCO The DCO is a power-efficient tunable internal oscillator that generates up to 48 MHz.
MSP432P401R, MSP432P401M www.ti.com 6.7.5 SLAS826 – MARCH 2015 System Controller (SYSCTL) The SYSCTL is a set of various miscellaneous features of the device, including SRAM bank configuration, RSTn/NMI function selection, and peripheral halt control. In addition, the SYSCTL enables device security features like JTAG and SWD lock and IP protection, which can be used to protect unauthorized accesses either to the entire device memory map or to certain selected regions of the flash.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com NOTE The glitch filter is implemented on the following digital I/Os on MSP432P401x devices: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7. 6.8.1.1.1 Digital I/O Glitch Filter Control Register [Address = E004_0030h] Figure 6-14.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 6-19.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-20. Default Mapping (continued) PIN NAME PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION P3.3/PM_UCA2TXD/ PM_UCA2SIMO PM_UCA2TXD/ PM_UCA2SIMO eUSCI_A2 UART TXD (direction controlled by eUSCI – output)/ eUSCI_A2 SPI slave in master out (direction controlled by eUSCI) P3.4/PM_UCB2STE PM_UCB2STE eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI) P3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 NOTE Internal signals that are sourced by the Timer outputs may connect to other modules (other Timers, ADC, etc) in the device (as trigger sources). Table 6-21. TA0 Signal Connections MODULE INPUT SIGNAL P7.1/PM_C0OUT/PM_TA0CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK C0OUT (internal) INCLK P7.3/PM_TA0.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-22. TA1 Signal Connections DEVICE INPUT PIN OR INTERNAL SIGNAL MODULE INPUT SIGNAL P7.2/PM_C1OUT/PM_TA1CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK PRODUCT PREVIEW 92 C1OUT (internal) INCLK P8.0/UCB3STE/TA1.0/C0.1 CCI0A DVSS CCI0B DVSS GND DVCC VCC P7.7/PM_TA1.1/C0.2 CCI1A ACLK (internal) CCI1B DVSS GND DVCC VCC P7.6/PM_TA1.2/C0.3 CCI2A C0OUT (internal) CCI2B DVSS GND DVCC VCC P7.5/PM_TA1.3/C0.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 DEVICE INPUT PIN OR INTERNAL SIGNAL MODULE INPUT SIGNAL P4.2/ACLK/TA2CLK/A11 TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK From Capacitive Touch I/O 0 (internal) INCLK P8.1/UCB3CLK/TA2.0/C0.0 CCI0A DVSS CCI0B DVSS GND DVCC VCC P5.6/TA2.1/VREF+/VeREF+/C1.7 CCI1A ACLK (internal) CCI1B DVSS GND DVCC VCC P5.7/TA2.2/VREF-/VeREF-/C1.6 CCI2A C0OUT (internal) CCI2B DVSS GND DVCC VCC P6.6/TA2.3/UCB3SIMO/UCB3SDA/C 1.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-24. TA3 Signal Connections DEVICE INPUT PIN OR INTERNAL SIGNAL MODULE INPUT SIGNAL P8.3/TA3CLK/A22 TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK From Capacitive Touch I/O 1 (internal) INCLK P10.4/TA3.0/C0.7 CCI0A DVSS CCI0B DVSS GND DVCC VCC P10.5/TA3.1/C0.6 CCI1A ACLK (internal) CCI1B DVSS GND PRODUCT PREVIEW DVCC VCC P8.2/TA3.2/A23 CCI2A C0OUT (internal) CCI2B DVSS GND DVCC VCC P9.2/TA3.
MSP432P401R, MSP432P401M www.ti.com 6.8.7 SLAS826 – MARCH 2015 Watchdog Timer (WDT_A) The primary function of the WDT_A module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com CAUTION The WDT should ideally be configured to generate a Hard Reset into the system. A Soft Reset will reset the CPU, but leave the rest of the system and peripherals unaffected. As a result if the WDT is configured to generate a Soft Reset, the application should assume responsibility for the fact that a Soft Reset can corrupt an ongoing transaction from the CPU into the system. 6.8.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 6-29.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.8.13 True Random Seed The Device Descriptor Information (TLV) section contains a 128-bit true random seed that can be used to implement a deterministic random number generator. 6.9 Code Development and Debug The MSP432P401x devices support various methods through which the user can carry out code development and debug on the device. 6.9.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 6-31.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.10 Input/Output Schematics 6.10.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger Pad Logic PyREN.x PyDIR.x From module 00 01 Direction 0: Input 1: Output 10 11 PyOUT.x DVSS 0 DVCC 1 1 00 From module 01 DVSS 10 DVSS 11 Py.x/USCI PRODUCT PREVIEW PySEL1.x PySEL0.x PyIN.x EN To module D Functional representation only. Figure 6-17. Py.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 6-32. Port P1 (P1.0 to P1.7) Pin Functions P1.0/UCA0STE P1.1/UCA0CLK P1.2/UCA0RXD/UCA0SOMI x 0 1 2 FUNCTION CONTROL BITS OR SIGNALS (1) P1DIR.x P1SEL1.x P1SEL0.x P1.0 (I/O) I: 0; O: 1 0 0 UCA0STE X (2) 0 1 1 0 1 1 N/A 0 DVSS 1 N/A 0 DVSS 1 P1.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-32. Port P1 (P1.0 to P1.7) Pin Functions (continued) PIN NAME (P1.x) P1.7/UCB0SOMI/UCB0SCL x 7 FUNCTION P1.7 (I/O) CONTROL BITS OR SIGNALS (1) P1DIR.x P1SEL1.x P1SEL0.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.2 Port P2, P2.0 to P2.3, Input/Output With Schmitt Trigger Pin Schematic: see Figure 6-17 Table 6-33. Port P2 (P2.0 to P2.3) Pin Functions P2.0/PM_UCA1STE x 0 FUNCTION P2.0 (I/O) UCA1STE P2.1/PM_UCA1CLK P2.2/PM_UCA1RXD/PM_U CA1SOMI P2.3/PM_UCA1TXD/PM_U CA1SIMO (1) (2) 1 2 P2DIR.x P2SEL1.x P2SEL0.x P2MAPx I: 0; O: 1 0 0 X 0 1 default 1 0 X 1 1 X X (2) N/A 0 DVSS 1 N/A 0 DVSS 1 P2.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.10.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger Pin Schematic: see Figure 6-17 Table 6-34. Port P3 (P3.0 to P3.7) Pin Functions PIN NAME (P3.x) P3.0/PM_UCA2STE x 0 FUNCTION P3.0 (I/O) UCA2STE P3.1/PM_UCA2CLK PRODUCT PREVIEW P3.2/PM_UCA2RXD/PM_U CA2SOMI P3.3/PM_UCA2TXD/PM_U CA2SIMO P3.4/PM_UCB2STE P3.5/PM_UCB2CLK 1 2 5 104 P3SEL0.x P3MAPx 0 0 X 0 1 default 1 0 X 1 1 X X (2) DVSS 1 N/A 0 DVSS 1 P3.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 6-34. Port P3 (P3.0 to P3.7) Pin Functions (continued) PIN NAME (P3.x) x P3.6/PM_UCB2SIMO/PM_ UCB2SDA 6 P3.6 (I/O) UCB2SIMO/UCB2SDA 7 CONTROL BITS OR SIGNALS (1) P3DIR.x P3SEL1.x P3SEL0.x I: 0; O: 1 0 0 X X (3) 0 1 default 1 0 X 1 1 X I: 0; O: 1 0 0 X X (3) 0 1 default 1 0 X 1 1 X N/A 0 DVSS 1 N/A 0 DVSS 1 P3.7 (I/O) UCB2SOMI/UCB2SCL N/A 0 DVSS 1 N/A 0 DVSS 1 P3MAPx PRODUCT PREVIEW P3.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.10.4 Port P9, P9.4 to P9.7, Input/Output With Schmitt Trigger Pin Schematic: see Figure 6-17 Table 6-35. Port P9 (P9.4 to P9.7) Pin Functions PIN NAME (P9.x) P9.4/UCA3STE (2) x 4 FUNCTION P9.4 (I/O) CONTROL BITS OR SIGNALS (1) P9DIR.x P9SEL1.x P9SEL0.x I: 0; O: 1 0 0 0 1 1 0 1 1 UCA3STE P9.5/UCA3CLK (2) PRODUCT PREVIEW P9.6/UCA3RXD/UCA3SOMI (2) 5 6 X N/A 0 DVSS 1 N/A 0 DVSS 1 P9.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.5 Port P10, P10.0 to P10.3, Input/Output With Schmitt Trigger Pin Schematic: see Figure 6-17 Table 6-36. Port P10 (P10.0 to P10.3) Pin Functions P10.0/UCB3STE (2) x 0 FUNCTION P10.0 (I/O) CONTROL BITS OR SIGNALS (1) P10DIR.x P10SEL1.x P10SEL0.x I: 0; O: 1 0 0 0 1 1 0 1 1 UCB3STE P10.1/UCB3CLK (2) P10.2/UCB3SIMO/UCB3SDA (2) 1 2 X N/A 0 DVSS 1 N/A 0 DVSS 1 P10.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.10.6 Port P2, P2.4 to P2.7, Input/Output With Schmitt Trigger Pad Logic PyREN.x PyDIR.x 00 01 Direction 0: Input 1: Output 10 11 PyOUT.x DVSS 0 DVCC 1 1 00 From module 01 DVSS 10 DVSS 11 Py.x/Mod1/Mod2 PySEL1.x PRODUCT PREVIEW PySEL0.x PyIN.x EN To module D Functional representation only. Figure 6-18. Py.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 6-37. Port P2 (P2.4 to P2.7) Pin Functions P2.4/PM_TA0.1 (2) P2.5/PM_TA0.2 (2) P2.6/PM_TA0.3 (2) P2.7/PM_TA0.4 (2) (1) (2) x 4 5 6 7 FUNCTION P2.4 (I/O) CONTROL BITS OR SIGNALS (1) P2DIR.x P2SEL1.x P2SEL0.x P2MAPx I: 0; O: 1 0 0 X 0 1 default 1 0 X 1 1 X 0 0 X 0 1 default 1 0 X 1 1 X 0 0 X 0 1 default 1 0 X 1 1 X 0 0 X 0 1 default 1 0 X 1 1 X TA0.CCI1A 0 TA0.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.10.7 Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger Pin Schematic: see Figure 6-18 Table 6-38. Port P7 (P7.0 to P7.3) Pin Functions PIN NAME (P7.x) P7.0/PM_SMCLK/ PM_DMAE0 P7.1/PM_C0OUT/ PM_TA0CLK PRODUCT PREVIEW P7.2/PM_C1OUT/ PM_TA1CLK P7.3/PM_TA0.0 (1) 110 x 0 1 2 3 FUNCTION P7.0 (I/O) CONTROL BITS OR SIGNALS (1) P7DIR.x P7SEL1.x P7SEL0.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.8 Port P9, P9.2 and P9.3, Input/Output With Schmitt Trigger Pin Schematic: see Figure 6-18 Table 6-39. Port P9 (P9.2 and P9.3) Pin Functions P9.2/TA3.3 (1) P9.3/TA3.4 (1) (1) x 2 3 FUNCTION P9.2 (I/O) CONTROL BITS OR SIGNALS P9DIR.x P9SEL1.x P9SEL0.x I: 0; O: 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 TA3.CCI3A 0 TA3.3 1 N/A 0 DVSS 1 N/A 0 DVSS 1 P9.3 (I/O) I: 0; O: 1 TA3.CCI4A 0 TA3.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.10.9 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic To ADC From ADC PyREN.x PyDIR.x 00 01 10 Direction 0: Input 1: Output 11 PyOUT.x 0 DVCC 1 1 00 PRODUCT PREVIEW † 01 From module 2 † 10 DVSS 11 From module 1 DVSS Py.x/Mod1/Mod2/Az PySEL1.x PySEL0.x PyIN.x EN To modules † Bus Keeper D Output will be DVSS if module 1 or module 2 function is not available. Refer to pin function tables.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 6-40. Port P4 (P4.0 to P4.7) Pin Functions P4.0/A13 (2) x 0 FUNCTION P4.0 (I/O) CONTROL BITS OR SIGNALS (1) P4DIR.x P4SEL1.x P4SEL0.x I: 0; O: 1 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 N/A 0 DVSS 1 N/A 0 DVSS 1 A13 (3) P4.1/A12 (2) P4.2/ACLK/TA2CLK/A11 P4.3/MCLK/RTCCLK/A10 1 2 3 P4.1 (I/O) N/A 0 DVSS 1 N/A 0 DVSS 1 A12 (3) X 1 1 I: 0; O: 1 0 0 0 1 1 0 P4.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-40. Port P4 (P4.0 to P4.7) Pin Functions (continued) PIN NAME (P4.x) P4.7/A6 x 7 FUNCTION P4.7 (I/O) CONTROL BITS OR SIGNALS (1) P4DIR.x P4SEL1.x P4SEL0.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.10 Port P5, P5.0 to P5.5, Input/Output With Schmitt Trigger Pin Schematic: see Figure 6-19 Table 6-41. Port P5 (P5.0 to P5.5) Pin Functions P5.0/A5 x 0 FUNCTION P5.0 (I/O) CONTROL BITS OR SIGNALS (1) P5DIR.x P5SEL1.x P5SEL0.x I: 0; O: 1 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 N/A 0 DVSS 1 N/A 0 DVSS 1 A5 (2) P5.1/A4 1 P5.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.10.11 Port P6, P6.0 and P6.1, Input/Output With Schmitt Trigger Pin Schematic: see Figure 6-19 Table 6-42. Port P6 (P6.0 and P6.1) Pin Functions PIN NAME (P6.x) P6.0/A15 (2) x 0 FUNCTION P6.0 (I/O) CONTROL BITS OR SIGNALS (1) P6DIR.x P6SEL1.x P6SEL0.x I: 0; O: 1 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 1 1 N/A 0 DVSS 1 N/A 0 DVSS 1 A15 (3) P6.1/A14 PRODUCT PREVIEW (1) (2) (3) 116 (2) 1 P6.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.12 Port P8, P8.2 to P8.7, Input/Output With Schmitt Trigger Pin Schematic: see Figure 6-19 Table 6-43. Port P8 (P8.2 to P8.7) Pin Functions P8.2/TA3.2/A23 (2) x 2 FUNCTION P8.2 (I/O) CONTROL BITS OR SIGNALS (1) P8DIR.x P8SEL1.x P8SEL0.x I: 0; O: 1 0 0 0 1 1 0 TA3.CCI2A 0 TA3.2 1 N/A 0 DVSS 1 A23 (3) P8.3/TA3CLK/A22 (2) 3 X 1 1 P8.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.10.13 Port P9, P9.0 and P9.1, Input/Output With Schmitt Trigger Pin Schematic: see Figure 6-19 Table 6-44. Port P9 (P9.0 and P9.1) Pin Functions PIN NAME (P9.x) P9.0/A17 (2) x 0 FUNCTION P9.0 (I/O) CONTROL BITS OR SIGNALS (1) P9DIR.x P9SEL1.x P9SEL0.x I: 0; O: 1 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 1 1 N/A 0 DVSS 1 N/A 0 DVSS 1 A17 (3) P9.1/A16 PRODUCT PREVIEW (1) (2) (3) 118 (2) 1 P9.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.14 Port P5, P5.6 and P5.7, Input/Output With Schmitt Trigger Pad Logic ADC Reference To Comparator From Comparator CPD.q PyREN.x 00 01 10 Direction 0: Input 1: Output 11 PyOUT.x DVSS 0 DVCC 1 1 00 From module 01 DVSS 10 DVSS 11 Py.x/Mod/VREF/VeREF/Cp.q PySEL1.x PySEL0.x PyIN.x Bus Keeper EN To module D Functional representation only. Figure 6-20. Py.x/Mod/VREF/VeREF/Cp.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-45. Port P5 (P5.6 and P5.7) Pin Functions PIN NAME (P5.x) x P5.6/TA2.1/VREF+/VeREF+/ C1.7 6 FUNCTION P5.6 (I/O) CONTROL BITS OR SIGNALS (1) P5DIR.x P5SEL1.x P5SEL0.x I: 0; O: 1 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 1 1 TA2.CCI1A 0 TA2.1 1 N/A 0 DVSS 1 VREF+, VeREF+, C1.7 (2) (3) P5.7/TA2.2/VREF-/VeREF/C1.6 (1) (2) PRODUCT PREVIEW (3) 120 7 P5.7 (I/O) TA2.CCI2A 0 TA2.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.15 Port P6, P6.2 to P6.5, Input/Output With Schmitt Trigger Pad Logic To Comparator From Comparator CPD.q PyREN.x From module 00 01 10 Direction 0: Input 1: Output 11 PyOUT.x DVSS 0 DVCC 1 1 00 From module 01 DVSS 10 DVSS 11 Py.x/USCI/Cp.q PySEL1.x PySEL0.x PyIN.x Bus Keeper EN To module D Functional representation only. Figure 6-21. Py.x/USCI/Cp.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-46. Port P6 (P6.2 to P6.5) Pin Functions PIN NAME (P6.x) P6.2/UCB1STE/C1.5 (2) P6.3/UCB1CLK/C1.4 (2) P6.4/UCB1SIMO/UCB1SDA/C1 .3 (2) PRODUCT PREVIEW P6.5/UCB1SOMI/UCB1SCL/C1. 2 (2) (1) (2) (3) (4) (5) 122 x 2 3 4 FUNCTION CONTROL BITS OR SIGNALS (1) P6DIR.x P6SEL1.x P6SEL0.x P6.2 (I/O) I: 0; O: 1 0 0 UCB1STE X (3) 0 1 1 0 N/A 0 DVSS 1 C1.5 (4) (5) X 1 1 P6.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.16 Port P6, P6.6 and P6.7, Input/Output With Schmitt Trigger Pad Logic To Comparator From Comparator CPD.q PyREN.x 00 01 From USCI 10 Direction 0: Input 1: Output 11 PyOUT.x 00 From module 01 From USCI 10 DVSS 11 DVSS 0 DVCC 1 1 Py.x/Mod/USCI/Cp.q PySEL1.x PySEL0.x PyIN.x Bus Keeper EN To modules D Functional representation only. Figure 6-22. Py.x/Mod/USCI/Cp.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-47. Port P6 (P6.6 and P6.7) Pin Functions PIN NAME (P6.x) x P6.6/TA2.3/UCB3SIMO/UCB 3SDA/C1.1 6 FUNCTION CONTROL BITS OR SIGNALS (1) P6DIR.x P6SEL1.x P6SEL0.x I: 0; O: 1 0 0 0 1 X (2) 1 0 C1.1 (3) (4) X 1 1 P6.7 (I/O) I: 0; O: 1 0 0 0 1 X (2) 1 0 X 1 1 P6.6 (I/O) TA2.CCI3A 0 TA2.3 1 UCB3SIMO/UCB3SDA P6.7/TA2.4/UCB3SOMI/UCB 3SCL/C1.0 7 TA2.CCI4A 0 TA2.4 1 UCB3SOMI/UCB3SCL C1.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.17 Port P8, P8.0 and P8.1, Input/Output With Schmitt Trigger Pad Logic To Comparator From Comparator CPD.q PyREN.x 00 01 10 Direction 0: Input 1: Output 11 PyOUT.x 00 From USCI 01 From module 10 DVSS 11 DVSS 0 DVCC 1 1 Py.x/USCI/Mod/Cp.q PySEL1.x PySEL0.x PyIN.x Bus Keeper EN To modules D Functional representation only. Figure 6-23. Py.x/USCI/Mod/Cp.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-48. Port P8 (P8.0 and P8.1) Pin Functions PIN NAME (P8.x) P8.0/UCB3STE/TA1.0/C0.1 P8.1/UCB3CLK/TA2.0/C0.0 (1) (2) (3) (4) PRODUCT PREVIEW 126 x 0 1 FUNCTION CONTROL BITS OR SIGNALS (1) P8DIR.x P8SEL1.x P8SEL0.x P8.0 (I/O) I: 0; O: 1 0 0 UCB3STE X (2) 0 1 TA1.CCI0A 0 TA1.0 1 1 0 C0.1 (3) (4) X 1 1 P8.1 (I/O) I: 0; O: 1 0 0 UCB3CLK X (2) 0 1 TA2.CCI0A 0 TA2.0 1 1 0 C0.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.18 Port P10, P10.4 and P10.5, Input/Output With Schmitt Trigger Pad Logic To Comparator From Comparator CPD.q PyREN.x 00 01 10 Direction 0: Input 1: Output 11 PyOUT.x 00 From module 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 1 Py.x/Mod/Cp.q PySEL1.x PySEL0.x PyIN.x Bus Keeper EN To module D Functional representation only. Figure 6-24. Py.x/Mod/Cp.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-49. Port P10 (P10.4 and P10.5) Pin Functions PIN NAME (P10.x) P10.4/TA3.0/C0.7 (2) x 4 FUNCTION CONTROL BITS OR SIGNALS (1) P10DIR.x P10SEL1.x P10SEL0.x P10.4 (I/O) I: 0; O: 1 0 0 TA3.CCI0A 0 TA3.0 1 0 1 N/A 0 DVSS 1 1 0 C0.7 (3) (4) P10.5/TA3.1/C0.6 (1) (2) (3) PRODUCT PREVIEW (4) 128 (2) 5 X 1 1 P10.5 (I/O) I: 0; O: 1 0 0 TA3.CCI1A 0 TA3.1 1 0 1 N/A 0 DVSS 1 1 0 C0.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.19 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger Pad Logic To Comparator From Comparator CPD.q PyMAP.x = PMAP_ANALOG PyREN.x PyDIR.x 00 DVSS 0 DVCC 1 1 01 Direction 0: Input 1: Output 10 11 00 From module 01 DVSS 10 DVSS 11 Py.x/Mod/Cp.q PySEL1.x PySEL0.x PyIN.x Bus Keeper EN To module D Functional representation only. Figure 6-25. Py.x/Mod/Cp.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-50. Port P7 (P7.4 to P7.7) Pin Functions PIN NAME (P7.x) P7.4/PM_TA1.4/C0.5 (2) x 4 FUNCTION P7.4 (I/O) P7.5/PM_TA1.3/C0.4 P7.6/PM_TA1.2/C0.3 PRODUCT PREVIEW P7.7/PM_TA1.1/C0.2 (1) (2) (3) (4) (5) 130 (2) (2) 5 6 7 P7DIR.x P7SEL1.x P7SEL0.x P7MAPx I: 0; O: 1 0 0 X 0 1 default 1 0 X X 1 1 X I: 0; O: 1 0 0 X 0 1 default 1 0 X TA1.CCI4A 0 TA1.4 1 N/A 0 DVSS 1 C0.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.20 Port PJ, PJ.0 and PJ.1 Input/Output With Schmitt Trigger Pad Logic To LFXT XIN PJREN.0 00 01 10 Direction 0: Input 1: Output 11 PJOUT.0 00 DVSS 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 1 PJ.0/LFXIN PRODUCT PREVIEW PJDIR.0 PJSEL0.0 PJSEL1.0 PJIN.0 Bus Keeper EN To modules D Functional representation only.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Pad Logic To LFXT XOUT PJSEL0.0 PJSEL1.0 LFXTBYPASS PJREN.1 PJDIR.1 00 01 10 Direction 0: Input 1: Output 11 PJOUT.1 00 DVSS 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 1 PJ.1/LFXOUT PRODUCT PREVIEW PJSEL0.1 PJSEL1.1 PJIN.1 EN To modules Bus Keeper D Functional representation only.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Table 6-51. Port PJ (PJ.0 and PJ.1) Pin Functions PJ.0/LFXIN x 0 FUNCTION PJ.0 (I/O) PJSEL1.0 PJSEL0.0 LFXT BYPASS I: 0; O: 1 X X 0 0 X X X 1 X X X X X 0 1 0 X X X 0 1 1 0 0 1 X X X 1 (2) (2) 1 I: 0; O: 1 N/A 0 DVSS 1 LFXOUT crystal mode (3) (4) PJSEL0.1 0 PJ.1 (I/O) (1) (2) PJSEL1.1 DVSS LFXIN bypass mode PJ.1/LFXOUT PJDIR.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.10.21 Port PJ, PJ.2 and PJ.3 Input/Output With Schmitt Trigger Pad Logic To HFXT XIN PJREN.3 PJDIR.3 00 01 10 Direction 0: Input 1: Output 11 PRODUCT PREVIEW PJOUT.3 00 DVSS 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 1 PJ.3/HFXIN PJSEL0.3 PJSEL1.3 PJIN.3 EN To modules Bus Keeper D Functional representation only.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 Pad Logic To HFXT XOUT PJSEL0.3 PJSEL1.3 HFXTBYPASS PJREN.2 PJDIR.2 00 01 10 Direction 0: Input 1: Output 11 PJOUT.2 00 DVSS 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 1 PJ.2/HFXOUT PRODUCT PREVIEW PJSEL0.2 PJSEL1.2 PJIN.2 Bus Keeper EN To modules D Functional representation only.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-52. Port PJ (PJ.2 and PJ.3) Pin Functions CONTROL BITS OR SIGNALS PIN NAME (PJ.x) PJ.3/HFXIN x 3 FUNCTION PJ.3 (I/O) (2) (2) PJSEL0.3 HFXT BYPASS I: 0; O: 1 X X 0 0 X X X 1 X X X X X 0 1 0 X X X 0 1 1 0 0 1 X X X 2 I: 0; O: 1 0 DVSS 1 PRODUCT PREVIEW HFXOUT crystal mode 136 PJSEL1.3 1 N/A (3) (4) PJSEL0.2 0 PJ.2 (I/O) (1) (2) PJSEL1.2 DVSS HFXIN bypass mode PJ.2/HFXOUT PJDIR.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.10.22 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger Table 6-53. Port PJ (PJ.4 to PJ.5) Pin Functions x PJ.4/TDI/ADC14CLK (2) , 4 FUNCTION PJ.4 (I/O) TDI (5) (4) , 5 PJSEL0.x PJMAPx I: 0; O: 1 0 0 X X (3) JTAG (4 wire) ADC12CLK 1 1 0 X X DVcc X 1 1 X X I: 0; O: 1 0 0 X X X 0 1 X 1 X PJ.5 (I/O) Hi-Z default SWJ MODE OF OPERATION (1) 1 SWO (5) PJSEL1.x 0 TDO (1) (2) (3) (4) PJDIR.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 6.10.23 Ports SWCLKTCK and SWDIOTMS With Schmitt Trigger Table 6-54. Ports SWCLKTCK and SWDIOTMS Pin Functions PIN NAME SWCLKTCK SWDIOTMS (1) (2) (1) (2) FUNCTION SWJ MODE OF OPERATION TCK (input) JTAG (4 wire) SWCLK (input) SWD (2 wire) TMS (input) JTAG (4 wire) SWDIO (I/O) SWD (2 wire) This pin is internally pulled to DVSS. This pin is internall pulled to DVCC.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 6.11 Device Descriptors (TLV) Table 6-56 lists the contents of the device descriptor tag-length-value (TLV) structure for MSP432P401xx devices. Table 6-55 summarizes the Device IDs of the corresponding MSP432P401xx devices. Table 6-55. Device IDs DEVICE DEVICE ID MSP432P401RIPZ 0000A000h MSP432P401MIPZ 0000A001h MSP432P401RIZXH 0000A002h MSP432P401MIZXH 0000A003h MSP432P401RIRGC 0000A004h MSP432P401MIRGC 0000A005h Table 6-56.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com Table 6-56.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 7 Applications, Implementation, and Layout 7.1 Device Connection and Layout Fundamentals This section discusses the recommended guidelines when designing with the MSP432™ microcontrollers. These guidelines are to make sure that the device has proper connections for powering, programming, debugging, and optimum analog performance. 7.1.1 Power Supply Decoupling and Bulk Capacitors TI recommends connecting a combination of a 4.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 7.1.3 www.ti.com General Layout Recommendations • • • • • 7.1.4 Proper grounding and short traces for external crystal to reduce parasitic capacitance. See the application report MSP430 32-kHz Crystal Oscillators (SLAA322) for recommended layout guidelines. Proper bypass capacitors on DVCC, AVCC, and reference pins if used. Avoid routing any high-frequency signal close to an analog signal line.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage enters the device. In this case, the 5-µF capacitor is used to buffer the reference pin and filter any lowfrequency ripple. A 50-nF bypass capacitor is used to filter out any high-frequency noise. 7.2.1.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 8 Device and Documentation Support 8.1 Device Support 8.1.1 Development Tools Support All MSP432 microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp432. 8.1.1.1 Hardware Features FAMILY JTAG SWD NUMBER OF BREAKPOINTS ITM DWT FPB MSP432P4xx Yes Yes 4 Yes Yes Yes 8.1.1.2 Recommended Hardware Options 8.1.
MSP432P401R, MSP432P401M www.ti.com 8.1.2 SLAS826 – MARCH 2015 Device and Development Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP432 MCU devices and support tools. Each MSP432 MCU commercial family member has one of three prefixes: MSP, PMS, or XMS (for example, MSP432P401R). Texas Instruments recommends two of three possible prefix designators for its support tools: MSP and MSPX.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.
MSP432P401R, MSP432P401M www.ti.com 8.2.2 SLAS826 – MARCH 2015 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com 9 Mechanical, Packaging, and Orderable Information 9.1 Packaging Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 PRODUCT PREVIEW www.ti.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com PACKAGE OUTLINE ZXH 80 (NFBGA - 1 mm max height) BALL GRID ARRAY 5.1 4.9 B A BALL A1 CORNER INDEX AREA 5.1 4.9 PRODUCT PREVIEW 0.7 0.6 C 1 MAX SEATING PLANE 0.08 C BALL TYP 0.25 TYP 0.15 4 TYP SYMM J H G F 4 TYP SYMM E D C B A 0.5 TYP 1 2 3 4 5 6 7 8 9 80X 0.35 0.25 0.15 0.05 C B C A 0.5 TYP 4221325/A 01/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis is for reference only.
MSP432P401R, MSP432P401M www.ti.com SLAS826 – MARCH 2015 EXAMPLE BOARD LAYOUT ZXH 80 (NFBGA - 1 mm max height) 80 BALL GRID ARRAY (0.5) TYP 0.265 0.235 1 2 3 4 5 6 7 8 9 A (0.5) TYP B C D SYMM E F PRODUCT PREVIEW G H J SYMM LAND PATTERN EXAMPLE SCALE:15X 0.05 MAX ( 0.25) METAL METAL UNDER MASK 0.05 MIN ( 0.25) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221325/A 01/2014 NOTES: (continued) 3.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.com EXAMPLE STENCIL DESIGN ZXH 80 (NFBGA - 1 mm max height) BALL GRID ARRAY (0.5) TYP (R0.05) TYP 80X ( 0.25) 1 (0.5) TYP 2 3 4 5 6 7 8 9 A B C METAL TYP D PRODUCT PREVIEW SYMM E F G H J SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:20X 4221325/A 01/2014 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 PRODUCT PREVIEW www.ti.
MSP432P401R, MSP432P401M SLAS826 – MARCH 2015 www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 24-Mar-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) XMS432P401MIPZR PREVIEW LQFP PZ 100 1000 TBD Call TI Call TI -40 to 85 XMS432P401RIPZR ACTIVE LQFP PZ 100 1000 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PACKAGE OPTION ADDENDUM www.ti.com 24-Mar-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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