Datasheet

P2.1/L25
35
P2.0/L24
36
P6.3/L19
37
P6.2/L18
38
P6.1/L17
39
P6.0/L16
40
P3.7/L15
41
P3.6/L14
42
P3.5/L13
43
P3.4/L12
44
P3.3/L11
45
P3.2/L10
46
P3.1/L9
47
P3.0/L8
48
TEST/SBWTCK
15
P4.0/TA1.1
16
P1.7/TA0.1/TDO/A7
17
P1.6/TA0.2/TDI/TCLK/A6
18
P1.5/TA0CLK/TMS/A5
19
20
P1.3/UCA0STE/A3
21
P1.2/UCA0CLK/A2
22
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+
23
P1.0/UCA0TXD/UCA0SIMO/A0/Veref–
24
P4.5/R33
7
P4.4/LCDCAP1
8
P4.3/LCDCAP0
9
P4.2/XOUT
10
P4.1/XIN
11
DVSS
12
DVCC
13
RST/NMI/SBWTDIO
14
P5.3/UCB0SOMI/UCB0SCL/L35
25
P5.2/UCB0SIMO/UCB0SDA/L34
26
P5.1/UCB0CLK/L33
27
P5.0/UCB0STE/L32
28
P2.7/L31
29
P2.6/L30
30
P2.5/L29
31
P2.4/L28
32
P2.3/L27
33
P2.2/L26
34
P7.3/L3
1
P7.2/L2
2
P7.1/L1
3
P7.0/L0
4
P4.7/R13
5
P4.6/R23
6
P1.4/MCLK/TCK/A4/VREF+
MSP430FR4133, MSP430FR4132, MSP430FR4131
www.ti.com SLAS865B –OCTOBER 2014–REVISED AUGUST 2015
Figure 4-3 shows the pinout of the 48-pin DGG package.
Figure 4-3. 48-Pin DGG (TSSOP) Designation
Copyright © 2014–2015, Texas Instruments Incorporated Terminal Configuration and Functions 9
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Product Folder Links: MSP430FR4133 MSP430FR4132 MSP430FR4131