Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015 www.ti.com
Table 6-47. LCD Registers (Base Address: 0600h) (continued)
REGISTER DESCRIPTION REGISTER OFFSET
Blinking memory for Static and 2 to 4 mux modes
LCD blinking memory 0 LCDBM0 40h
LCD blinking memory 1 LCDBM1 41h
⋮ ⋮ ⋮
LCD blinking memory 19 LCDBM19 53h
Reserved
(1)
54h
⋮ ⋮ ⋮
Reserved
(1)
5Fh
Display memory for 5 to 8 mux modes
LCD memory 0 LCDM0 20h
LCD memory 1 LCDM1 21h
LCD memory 2 LCDM2 22h
⋮ ⋮ ⋮
LCD memory 39 LCDM39 47h
Reserved
(2)
48h
⋮ ⋮ ⋮
Reserved
(2)
5Fh
(2) In 5-mux to 8-mux modes, LCD memory and blink memory 40 to 63 are not physically implemented.
Table 6-48. Backup Memory Registers (Base Address: 0660h)
REGISTER DESCRIPTION REGISTER OFFSET
Backup Memory 0 BAKMEM0 00h
Backup Memory 1 BAKMEM1 02h
Backup Memory 2 BAKMEM2 04h
Backup Memory 3 BAKMEM3 06h
Backup Memory 4 BAKMEM4 08h
Backup Memory 5 BAKMEM5 0Ah
Backup Memory 6 BAKMEM6 0Ch
Backup Memory 7 BAKMEM7 0Eh
Backup Memory 8 BAKMEM8 10h
Backup Memory 9 BAKMEM9 12h
Backup Memory 10 BAKMEM10 14h
Backup Memory 11 BAKMEM11 16h
Backup Memory 12 BAKMEM12 18h
Backup Memory 13 BAKMEM13 1Ah
Backup Memory 14 BAKMEM14 1Ch
Backup Memory 15 BAKMEM15 1Eh
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