Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
www.ti.com SLAS865B –OCTOBER 2014–REVISED AUGUST 2015
Table 6-46. eUSCI_B0 Registers (Base Address: 0540h)
REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_B control word 0 UCB0CTLW0 00h
eUSCI_B control word 1 UCB0CTLW1 02h
eUSCI_B bit rate 0 UCB0BR0 06h
eUSCI_B bit rate 1 UCB0BR1 07h
eUSCI_B status word UCB0STATW 08h
eUSCI_B byte counter threshold UCB0TBCNT 0Ah
eUSCI_B receive buffer UCB0RXBUF 0Ch
eUSCI_B transmit buffer UCB0TXBUF 0Eh
eUSCI_B I2C own address 0 UCB0I2COA0 14h
eUSCI_B I2C own address 1 UCB0I2COA1 16h
eUSCI_B I2C own address 2 UCB0I2COA2 18h
eUSCI_B I2C own address 3 UCB0I2COA3 1Ah
eUSCI_B receive address UCB0ADDRX 1Ch
eUSCI_B address mask UCB0ADDMASK 1Eh
eUSCI_B I2C slave address UCB0I2CSA 20h
eUSCI_B interrupt enable UCB0IE 2Ah
eUSCI_B interrupt flags UCB0IFG 2Ch
eUSCI_B interrupt vector word UCB0IV 2Eh
Table 6-47. LCD Registers (Base Address: 0600h)
REGISTER DESCRIPTION REGISTER OFFSET
LCD control register 0 LCDCTL0 00h
LCD control register 1 LCDCTL1 02h
LCD blink control register LCDBLKCTL 04h
LCD memory control register LCDMEMCTL 06h
LCD voltage control register LCDVCTL 08h
LCD port control 0 LCDPCTL0 0Ah
LCD port control 1 LCDPCTL1 0Ch
LCD port control 2 LCDPCTL2 0Eh
LCD COM/SEG select register LCDCSS0 14h
LCD COM/SEG select register LCDCSS1 16h
LCD COM/SEG select register LCDCSS2 18h
LCD interrupt vector LCDIV 1Eh
Display memory Static and 2 to 4 mux modes
LCD memory 0 LCDM0 20h
LCD memory 1 LCDM1 21h
LCD memory 2 LCDM2 22h
⋮ ⋮ ⋮
LCD memory 19 LCDM19 33h
Reserved
(1)
34h
⋮ ⋮ ⋮
Reserved
(1)
3Fh
(1) In static and 2-mux to 4-mux modes, LCD memory and blink memory 40 to 63 are not physically implemented.
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