Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
www.ti.com SLAS865B –OCTOBER 2014–REVISED AUGUST 2015
Table 6-39. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P5 input P5IN 00h
Port P5 output P5OUT 02h
Port P5 direction P5DIR 04h
Port P5 pulling register enable P5REN 06h
Port P5 selection 0 P5SEL0 0Ah
Port P6 input P6IN 01h
Port P6 output P6OUT 03h
Port P6 direction P6DIR 05h
Port P6 pulling register enable P6REN 07h
Port P6 selection 0
(1)
P6SEL0 0Bh
(1) Port P6 selection register does not feature any valid bits. P6SEL0 presents for 16-bit Port C operation with P5SEL0.
Table 6-40. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P7 input P7IN 00h
Port P7 output P7OUT 02h
Port P7 direction P7DIR 04h
Port P7 pulling register enable P7REN 06h
Port P7 selection 0
(1)
P7SEL0 0Ah
Port P8 input P8IN 01h
Port P8 output P8OUT 03h
Port P8 direction P8DIR 05h
Port P8 pulling register enable P8REN 07h
Port P8 selection 0 P8SEL0 0Bh
(1) Port P7 selection register does not feature any valid bits. P7SEL0 presents for 16-bit Port D operation with P8SEL0.
Table 6-41. Capacitive Touch IO Registers (Base Address: 02E0h)
REGISTER DESCRIPTION REGISTER OFFSET
Capacitive Touch IO 0 control CAPTIO0CTL 0Eh
Table 6-42. Timer0_A3 Registers (Base Address: 0300h)
REGISTER DESCRIPTION REGISTER OFFSET
TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 2 TA0CCTL2 06h
TA0 counter register TA0R 10h
Capture/compare register 0 TA0CCR0 12h
Capture/compare register 1 TA0CCR1 14h
Capture/compare register 2 TA0CCR2 16h
TA0 expansion register 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh
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