Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
www.ti.com SLAS865B –OCTOBER 2014–REVISED AUGUST 2015
Table 6-30. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION REGISTER OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h
Table 6-31. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION REGISTER OFFSET
PMM Control 0 PMMCTL0 00h
PMM Control 1 PMMCTL1 02h
PMM Control 2 PMMCTL2 04h
PMM interrupt flags PMMIFG 0Ah
PM5 Control 0 PM5CTL0 10h
Table 6-32. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION REGISTER OFFSET
System control SYSCTL 00h
Bootstrap loader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus Error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh
System configuration 0 SYSCFG0 20h
System configuration 1 SYSCFG1 22h
System configuration 2 SYSCFG2 24h
Table 6-33. CS Registers (Base Address: 0180h)
REGISTER DESCRIPTION REGISTER OFFSET
CS control register 0 CSCTL0 00h
CS control register 1 CSCTL1 02h
CS control register 2 CSCTL2 04h
CS control register 3 CSCTL3 06h
CS control register 4 CSCTL4 08h
CS control register 5 CSCTL5 0Ah
CS control register 6 CSCTL6 0Ch
CS control register 7 CSCTL7 0Eh
CS control register 8 CSCTL8 10h
Table 6-34. FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTION REGISTER OFFSET
FRAM control 0 FRCTL0 00h
General control 0 GCCTL0 04h
General control 1 GCCTL1 06h
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