Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015 www.ti.com
6.11.1 Peripheral File Map
Table 6-29 shows the base address and the memory size of the registers of each peripheral, and Table 6-
30 through Table 6-49 show all of the available registers for each peripheral and their address offsets.
Table 6-29. Peripherals Summary
MODULE NAME BASE ADDRESS SIZE
Special Functions (see Table 6-30) 0100h 0010h
PMM (see Table 6-31) 0120h 0020h
SYS (see Table 6-32) 0140h 0030h
CS (see Table 6-33) 0180h 0020h
FRAM (see Table 6-34) 01A0h 0010h
CRC (see Table 6-35) 01C0h 0008h
WDT (see Table 6-36) 01CCh 0002h
Port P1, P2 (see Table 6-37) 0200h 0020h
Port P3, P4 (see Table 6-38) 0220h 0020h
Port P5, P6 (see Table 6-39) 0240h 0020h
Port P7, P8 (see Table 6-40) 0260h 0020h
Capacitive Touch I/O (see Table 6-41) 02E0h 0010h
Timer0_A3 (see Table 6-42) 0300h 0030h
Timer1_A3 (see Table 6-43) 0340h 0030h
RTC (see Table 6-44) 03C0h 0010h
eUSCI_A0 (see Table 6-45) 0500h 0020h
eUSCI_B0 (see Table 6-46) 0540h 0030h
LCD (see Table 6-47) 0600h 0060h
Backup Memory (see Table 6-48) 0660h 0020h
ADC (see Table 6-49) 0700h 0040h
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