Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
www.ti.com SLAS865B –OCTOBER 2014–REVISED AUGUST 2015
Table 6-27. Device Descriptors (continued)
MSP430FR413x
DESCRIPTION
ADDRESS VALUE
Calibration Tag 1A1Eh 12h
Calibration Length 1A1Fh 04h
1A20h per unit
Reference and DCO Calibration 1.5-V Reference Factor
1A21h per unit
1A22h per unit
DCO Tap Settings for 16 MHz, Temperature
30°C
(2)
1A23h per unit
(2) This value can be directly loaded into DCO bits in CSCTL0 register to get accurate 16-MHz frequency at room temperature, especially
when MCU exits from LPM3 and below. It is also suggested to use predivider to decrease the frequency if the temperature drift might
result an overshoot beyond 16 MHz.
6.11 Memory
Table 6-28 shows the memory organization of the MSP430FR413x devices.
Table 6-28. Memory Organization
ACCESS MSP430FR4133 MSP430FR4132 MSP430FR4131
Memory (FRAM)
Read/Write 15KB 8KB 4KB
Main: interrupt vectors and
(Optional Write FFFFh-FF80h FFFFh-FF80h FFFFh-FF80h
signatures
Protect)
(1)
FFFFh-C400h FFFFh-E000h FFFFh-F000h
Main: code memory
2KB 1KB 512 B
RAM Read/Write
27FFh-2000h 23FFh-2000h 21FFh-2000h
Read/Write
512B 512B 512B
Information Memory (FRAM) (Optional Write
19FFh-1800h 19FFh-1800h 19FFh-1800h
Protect)
(2)
Bootstrap loader (BSL) Memory 1KB 1KB 1KB
Read only
(ROM) 13FFh-1000h 13FFh-1000h 13FFh-1000h
4KB 4KB 4KB
Peripherals Read/Write
0FFFh-0000h 0FFFh-0000h 0FFFh-0000h
(1) The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. Refer to the SYS chapter in the MSP430FR4xx
and MSP430FR2xx Family User's Guide (SLAU445) for more details.
(2) The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. Refer to the SYS chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445) for more details.
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