Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015 www.ti.com
Table 6-14. Port P1 Pin Functions
CONTROL BITS AND SIGNALS
(1)
PIN NAME (P1.x) x FUNCTION
P1DIR.x P1SEL0.x ADCPCTLx
(2)
JTAG
P1.0 (I/O) I: 0; O: 1 0 0 N/A
P1.0/UCA0TXD/
0 UCA0TXD/UCA0SIMO X 1 0 N/A
UCA0SIMO/A0
A0 X X 1 (x = 0) N/A
P1.1 (I/O) I: 0; O: 1 0 0 N/A
P1.1/UCA0RXD/
1 UCA0RXD/UCA0SOMI X 1 0 N/A
UCA0SOMI/A1
A1 X X 1 (x = 1) N/A
P1.2 (I/O) I: 0; O: 1 0 0 N/A
P1.2/UCA0CLK/A2 2 UCA0CLK X 1 0 N/A
A2 X X 1 (x = 2) N/A
P1.3 (I/O) I: 0; O: 1 0 0 N/A
P1.3/UCA0STE/A3 3 UCA0STE X 1 0 N/A
A3 X X 1 (x = 3) N/A
P1.4 (I/O) I: 0; O: 1 0 0 Disabled
VSS 0
1 0 Disabled
P1.4/MCLK/TCK/A4/
4 MCLK 1
VREF+
A4, VREF+ X X 1 (x = 4) Disabled
JTAG TCK X X X TCK
P1.5 (I/O) I: 0; O: 1 0 0 Disabled
TA0CLK 0
1 0 Disabled
P1.5/TA0CLK/TMS/A5 5 VSS 1
A5 X X 1 (x = 5) Disabled
JTAG TMS X X X TMS
P1.6 (I/O) I: 0; O: 1 0 0 Disabled
TA0.CCI2A 0
1 0 Disabled
P1.6/TA0.2/TDI/TCLK/
6 TA0.2 1
A6
A6 X X 1 (x = 6) Disabled
JTAG TDI/TCLK X X X TDI/TCLK
P1.7 (I/O) I: 0; O: 1 0 0 Disabled
TA0.CCI1A 0
1 0 Disabled
P1.7/TA0.1/TDO/A7 7 TA0.1 1
A7 X X 1 (x = 7) Disabled
JTAG TDO X X X TDO
(1) X = don't care
(2) Setting the ADCPCTLx bit in SYSCFG2 register will disable both the output driver and input Schmitt trigger to prevent leakage when
analog signals are applied.
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Product Folder Links: MSP430FR4133 MSP430FR4132 MSP430FR4131