Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015 www.ti.com
Table 6-11. Timer1_A3 Signal Connections
DEVICE INPUT MODULE INPUT MODULE OUTPUT DEVICE OUTPUT
PORT PIN MODULE BLOCK
SIGNAL NAME SIGNAL SIGNAL
P8.2 TA1CLK TACLK
ACLK (internal) ACLK
Timer N/A
SMCLK (internal) SMCLK
Timer0_A3 CCR2B
INCLK
output (internal)
CCI0A
Timer0_A3 CCR0B
CCI0B
output (internal)
CCR0 TA0
DVSS GND
DVCC VCC
P4.0 TA1.1 CCI1A TA1.1
Timer0_A3 CCR1B
CCI1B to ADC trigger
output (internal)
CCR1 TA1
DVSS GND
DVCC VCC
P8.3 TA1.2 CCI2A TA1.2
Timer0_A3 CCR2B
CCI2B IR Input
output (internal)
CCR2 TA2
DVSS GND
DVCC VCC
The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of
UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated
infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS
configuration registers 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select),
IRDSEL (data select), and IRDATA (data) bits. For more information, refer to the SYS chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445).
44 Detailed Description Copyright © 2014–2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR4133 MSP430FR4132 MSP430FR4131