Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
www.ti.com SLAS865B –OCTOBER 2014–REVISED AUGUST 2015
6.9.8 Timers (Timer0_A3, Timer1_A3)
The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare
registers each. Each can support multiple captures or compares, PWM outputs, and interval timing. Each
has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions
and from each of the capture/compare registers. The CCR0 registers on both TA0 and TA1 are not
externally connected and can only be used for hardware period timing and interrupt generation. In Up
Mode, they can be used to set the overflow value of the counter.
Table 6-10. Timer0_A3 Signal Connections
DEVICE INPUT MODULE INPUT MODULE OUTPUT DEVICE OUTPUT
PORT PIN MODULE BLOCK
SIGNAL NAME SIGNAL SIGNAL
P1.5 TA0CLK TACLK
ACLK (internal) ACLK
Timer N/A
SMCLK (internal) SMCLK
from Capacitive
INCLK
Touch IO (internal)
CCI0A
Timer1_A3 CCI0B
CCI0B
input
CCR0 TA0
DVSS GND
DVCC VCC
P1.7 TA0.1 CCI1A TA0.1
Timer1_A3 CCI1B
from RTC (internal) CCI1B
input
CCR1 TA1
DVSS GND
DVCC VCC
P1.6 TA0.2 CCI2A TA0.2
Timer1_A3 INCLK
from Capacitive Timer1_A3 CCI2B
CCI2B
Touch I/O (internal) input,
CCR2 TA2
IR Input
DVSS GND
DVCC VCC
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