Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015 www.ti.com
Table 6-8. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR
ADDRESS INTERRUPT EVENT VALUE PRIORITY
REGISTER
No interrupt pending 00h
SVS low-power reset entry 02h Highest
Uncorrectable FRAM bit error detection 04h
Reserved 06h
Reserved 08h
Reserved 0Ah
Reserved 0Ch
SYSSNIV, System NMI 015Ch
Reserved 0Eh
Reserved 10h
VMAIFG Vacant memory access 12h
JMBINIFG JTAG mailbox input 14h
JMBOUTIFG JTAG mailbox output 16h
Correctable FRAM bit error detection 18h
Reserved 1Ah to 1Eh Lowest
No interrupt pending 00h
NMIIFG NMI pin or SVS
H
event 02h Highest
SYSUNIV, User NMI 015Ah
OFIFG oscillator fault 04h
Reserved 06h to 1Eh Lowest
6.9.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data
values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x
16
+ x
12
+ x
5
+ 1.
6.9.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either
UART or SPI communications. The eUSCI_B module supports either SPI or I
2
C communications.
Additionally, eUSCI_A supports automatic baud-rate detection and IrDA.
Table 6-9. eUSCI Pin Configurations
PIN UART SPI
P1.0 TXD SIMO
eUSCI_A0 P1.1 RXD SOMI
P1.2 SCLK
P1.3 STE
PIN I
2
C SPI
P5.0 STE
eUSCI_B0 P5.1 SCLK
P5.2 SDA SIMO
P5.3 SCL SOMI
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