Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
www.ti.com SLAS865B –OCTOBER 2014–REVISED AUGUST 2015
6 Detailed Description
6.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
6.2 Operating Modes
The devices have one active mode and several software-selectable low-power modes of operation. An
interrupt event can wake up the device from low-power mode LPM0 or LPM3, service the request, and
restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and
LPM4.5 disable the core supply to minimize power consumption.
Table 6-1. Operating Modes
AM LPM0 LPM3 LPM4 LPM3.5 LPM4.5
ONLY RTC
MODE
ACTIVE
CPU OFF STANDBY OFF COUNTER SHUTDOWN
MODE
AND LCD
Maximum System Clock 16 MHz 16 MHz 40 kHz 0 40 kHz 0
0.6 µA 0.77 µA with 13 nA
Power Consumption at 25°C, 3 V 126 µA/MHz 20 µA/MHz 1.2 µA
without SVS RTC only without SVS
Wake-up time N/A Instant 10 µs 10 µs 150 µs 150 µs
RTC Counter
Wake-up events N/A All All I/O I/O
I/O
Full Full Partial Power Partial Power Partial Power
Regulator Power Down
Regulation Regulation Down Down Down
Power
SVS On On Optional Optional Optional Optional
Brown Out On On On On On On
MCLK Active Off Off Off Off Off
SMCLK Optional Optional Off Off Off Off
FLL Optional Optional Off Off Off Off
DCO Optional Optional Off Off Off Off
Clock MODCLK Optional Optional Off Off Off Off
REFO Optional Optional Optional Off Off Off
ACLK Optional Optional Optional Off Off Off
XT1CLK Optional Optional Optional Off Optional Off
VLOCLK Optional Optional Optional Off Optional Off
CPU On Off Off Off Off Off
FRAM On On Off Off Off Off
Core
RAM On On On On Off Off
Backup Memory
(1)
On On On On On Off
(1) Backup memory contains one 32-byte register in the peripheral memory space. Refer to Table 6-29 and Table 6-48 for its memory
allocation.
Copyright © 2014–2015, Texas Instruments Incorporated Detailed Description 35
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