Datasheet
MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015
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5.12.9 FRAM
Table 5-21. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Read and write endurance 10
15
cycles
T
J
= 25°C 100
t
Retention
Data retention duration T
J
= 70°C 40 years
T
J
= 85°C 10
5.12.10 Emulation and Debug
Table 5-22. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER V
CC
MIN TYP MAX UNIT
f
SBW
Spy-Bi-Wire input frequency 2 V, 3 V 0 10 MHz
t
SBW,Low
Spy-Bi-Wire low clock pulse duration 2 V, 3 V 0.028 15 µs
t
SBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
(1)
2 V, 3 V 110 µs
t
SBW,Rst
Spy-Bi-Wire return to normal operation time 15 100 µs
2 V 0 16 MHz
f
TCK
TCK input frequency, 4-wire JTAG
(2)
3 V 0 16 MHz
R
internal
Internal pulldown resistance on TEST 2 V, 3 V 20 35 50 kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the t
SBW,En
time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) f
TCK
may be restricted to meet the timing requirements of the module selected.
34 Specifications Copyright © 2014–2015, Texas Instruments Incorporated
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