Datasheet

SDA
SCL
t
HD,DAT
t
SU,DAT
t
HD,STA
t
HIGH
t
LOW
t
BUF
t
HD,STA
t
SU,STA
t
SP
t
SU,STO
MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015 www.ti.com
Table 5-16. eUSCI (I
2
C Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-14)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, MODCLK
f
eUSCI
eUSCI input clock frequency External: UCLK 16 MHz
Duty cycle = 50% ± 10%
f
SCL
SCL clock frequency 2 V, 3 V 0 400 kHz
f
SCL
= 100 kHz 4.0
t
HD,STA
Hold time (repeated) START 2 V, 3 V µs
f
SCL
> 100 kHz 0.6
f
SCL
= 100 kHz 4.7
t
SU,STA
Setup time for a repeated START 2 V, 3 V µs
f
SCL
> 100 kHz 0.6
t
HD,DAT
Data hold time 2 V, 3 V 0 ns
t
SU,DAT
Data setup time 2 V, 3 V 250 ns
f
SCL
= 100 kHz 4.0
t
SU,STO
Setup time for STOP 2 V, 3 V µs
f
SCL
> 100 kHz 0.6
UCGLITx = 0 50 600 ns
UCGLITx = 1 25 300 ns
Pulse duration of spikes suppressed by
t
SP
2 V, 3 V
input filter
UCGLITx = 2 12.5 150 ns
UCGLITx = 3 6.3 75 ns
UCCLTOx = 1 27 ms
t
TIMEOUT
Clock low time-out UCCLTOx = 2 2 V, 3 V 30 ms
UCCLTOx = 3 33 ms
Figure 5-14. I
2
C Mode Timing
30 Specifications Copyright © 2014–2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR4133 MSP430FR4132 MSP430FR4131