Datasheet
Cap Touch I/O
DVCC
RST/NMI
XIN
XOUT
P3.x/P4.x
P5.x/P6.x
P1.x/P2.x P7.x/P8.x
LPM3.5 Domain
SBWTDIO
SBWTCK
TDO
TDI/TCLK
TMS
TCK
DVSS
I/O Ports
P1/P2
2×8 IOs
Interrupt
& Wakeup
PA
1×16 IOs
ADC
Up to 10-ch
Single-end
10-bit
200ksps
Clock
System
Control
XT1
FRAM
15KB+512B
8KB+ B
4KB+ B
512
512
RAM
2KB
1KB
512B
Watchdog
SYS
TA1
Timer_A
3 CC
Registers
eUSCI_A0
(UART,
IrDA, SPI)
eUSCI_B0
(SPI, I2C)
CRC16
16-bit
Cyclic
Redundancy
Check
RTC
Counter
16-bit
Real-Time
Clock
LCD
4×36
8×32
Segments
JTAG
SBW
I/O Ports
P3/P4
2×8 IOs
PB
1×16 IOs
I/O Ports
P5/P6
2×8 IOs
PC
1×16 IOs
I/O Ports
P7/P8
1×8 IOs
PD
1×12 IOs
1×4 IOs
TA0
Timer_A
3 CC
Registers
EEM
MAB
MDB
16-MHZ CPU
inc.
16 Registers
Power
Management
Module
MSP430FR4133, MSP430FR4132, MSP430FR4131
www.ti.com
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram.
Figure 1-1. Functional Block Diagram
• The device has one main power pair of DVCC and DVSS that supplies both digital and analog
modules. Recommended bypass and decouple capacitors are 4.7 µF to 10 µF and 0.1 µF,
respectively, with ±5% accuracy.
• P1 and P2 feature the pin-interrupt function and can wake the MCU from LPM3.5.
• Each Timer_A3 has three CC registers, but only the CCR1 and CCR2 are externally connected. CCR0
registers can only be used for internal period timing and interrupt generation.
• In LPM3.5, the RTC counter and the LCD can be functional while the rest of peripherals are off.
• All I/Os can be configured as Capacitive Touch I/Os.
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Product Folder Links: MSP430FR4133 MSP430FR4132 MSP430FR4131