Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015 www.ti.com
5.12.6 eUSCI
Table 5-11. eUSCI (UART Mode) Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
Internal: SMCLK, MODCLK
f
eUSCI
eUSCI input clock frequency External: UCLK 2 V, 3 V 16 MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
f
BITCLK
2 V, 3 V 5 MHz
(equals baud rate in Mbaud)
Table 5-12. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
TYP UNIT
UCGLITx = 0 12
UCGLITx = 1 40
t
t
UART receive deglitch time
(1)
2 V, 3 V ns
UCGLITx = 2 68
UCGLITx = 3 110
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
Table 5-13. eUSCI (SPI Master Mode) Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER CONDITIONS MIN MAX UNIT
Internal: SMCLK, MODCLK
f
eUSCI
eUSCI input clock frequency 8 MHz
Duty cycle = 50% ± 10%
Table 5-14. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
UCxCLK
t
STE,LEAD
STE lead time, STE active to clock UCSTEM = 1, UCMODEx = 01 or 10 1
cycles
STE lag time, Last clock to STE UCxCLK
t
STE,LAG
UCSTEM = 1, UCMODEx = 01 or 10 1
inactive cycles
2 V 45
t
SU,MI
SOMI input data setup time ns
3 V 35
2 V 0
t
HD,MI
SOMI input data hold time ns
3 V 0
2 V 20
UCLK edge to SIMO valid,
t
VALID,MO
SIMO output data valid time
(2)
ns
C
L
= 20 pF
3 V 20
2 V 0
t
HD,MO
SIMO output data hold time
(3)
C
L
= 20 pF ns
3 V 0
(1) f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
= max(t
VALID,MO(eUSCI)
+ t
SU,SI(Slave)
, t
SU,MI(eUSCI)
+ t
VALID,SO(Slave)
).
For the slave parameters t
SU,SI(Slave)
and t
VALID,SO(Slave)
refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-10 and Figure 5-11.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 5-10 and Figure 5-11.
26 Specifications Copyright © 2014–2015, Texas Instruments Incorporated
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