Datasheet

VBOR
VSVS–
VSVS+
t
V
Power Cycle Reset SVS Reset
BOR Reset
tBOR
MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015 www.ti.com
5.12 Timing and Switching Characteristics
5.12.1 Power Supply Sequencing
Figure 5-5. Power Cycle, SVS, and BOR Reset Conditions
Table 5-1. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
BOR, safe
Safe BOR power-down level
(1)
0.1 V
t
BOR, safe
Safe BOR reset delay
(2)
10 ms
I
SVSH,AM
SVS
H
current consumption, active mode V
CC
= 3.6 V 1.5 µA
I
SVSH,LPM
SVS
H
current consumption, low-power modes V
CC
= 3.6 V 240 nA
V
SVSH-
SVS
H
power-down level 1.71 1.81 1.87 V
V
SVSH+
SVS
H
power-up level 1.76 1.88 1.99 V
V
SVSH_hys
SVS
H
hysteresis 70 mV
t
PD,SVSH, AM
SVS
H
propagation delay, active mode 10 µs
t
PD,SVSH, LPM
SVS
H
propagation delay, low-power modes 100 µs
V
REF, 1.2V
1.2-V REF voltage
(3)
1.158 1.20 1.242 V
(1) A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.
(2) When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches V
SVSH+
.
(3) This is a characterized result with external 1-mA load to ground from –40°C to +85°C.
20 Specifications Copyright © 2014–2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR4133 MSP430FR4132 MSP430FR4131