Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015 www.ti.com
5 Specifications
5.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage applied at DVCC pin to V
SS
–0.3 4.1 V
V
CC
+ 0.3
Voltage applied to any pin
(2)
–0.3 V
(4.1 Max)
Diode current at any device pin ±2 mA
Maximum junction temperature, T
J
85 °C
Storage temperature, T
stg
(3)
–40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±1000
V
(ESD)
Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
Typical values are specified at V
CC
= 3.3 V and T
A
= 25°C (unless otherwise noted)
MIN NOM MAX UNIT
V
CC
Supply voltage applied at DVCC pin
(1)(2)(3)
1.8 3.6 V
V
SS
Supply voltage applied at DVSS pin 0 V
T
A
Operating free-air temperature –40 85 °C
T
J
Operating junction temperature –40 85 °C
C
DVCC
Recommended capacitor at DVCC
(4)
4.7 10 µF
No FRAM wait states
0 8
(NWAITSx = 0)
f
SYSTEM
Processor frequency (maximum MCLK frequency)
(3)(5)
MHz
With FRAM wait states
0 16
(7)
(NWAITSx = 1)
(6)
f
ACLK
Maximum ACLK frequency 40 kHz
f
SMCLK
Maximum SMCLK frequency 16
(7)
MHz
(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range.
(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) The minimum supply voltage is defined by the SVS levels. Refer to the SVS threshold parameters in Table 5-1.
(4) A capacitor tolerance of ±20% or better is required.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(6) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
(7) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
14 Specifications Copyright © 2014–2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR4133 MSP430FR4132 MSP430FR4131